Document Outline

• 1. Preface
  • 1.1. About This Document
  • 1.2. Intended Audience
  • 1.3. No special word usage
  • 1.4. No statements of compliance
  • 1.5. Correctness Disclaimer
  • 1.6. Name and logo usage
  • 1.7. Intellectual property
  • 1.8. Acronyms, Abbreviations and Definitions Used
  • 1.9. Signal Table Terminology
  • 1.10. Schematic Conventions
• 2. COM Express Interfaces
  • 2.1. COM Express Signals
    • 2.1.1. Connector Pin-out Comparison
  • 2.2. PCIe General Introduction
    • 2.2.1. COM Express A-B Connector and C-D Connector PCIe Groups
  • 2.3. General Purpose PCIe Lanes
    • 2.3.1. General Purpose PCIe Signal Definitions
    • 2.3.2. PCI Express Lane Configurations – Per COM Express Spec
    • 2.3.3. PCI Express Lane Configurations – Module and Chipset Dependencies
    • 2.3.4. Device Up / Device Down and PCIe Rx / Tx Coupling Capacitors
    • 2.3.5. Schematic Examples
      • 2.3.5.1. Reference Clock Buffer
      • 2.3.5.2. Reset
      • 2.3.5.3. x1 Slot Example
      • 2.3.5.4. x4 Slot Example
      • 2.3.5.5. PCIe x1 Generic Device Down Example
      • 2.3.5.6. PCIe x4 Generic Device Down Example
      • 2.3.5.7. PCI Express Mini Card
      • 2.3.5.8. ExpressCard
    • 2.3.6. PCI Express Routing Considerations
      • 2.3.6.1. Polarity Inversion
      • 2.3.6.2. Lane Reversal
  • 2.4. PEG (PCI Express Graphics)
    • 2.4.1. Signal Definitions
    • 2.4.2. PEG Configuration
      • 2.4.2.1. Using PEG Pins for an External Graphics Card
      • 2.4.2.2. Using PEG Pins for SDVO (Type 2 Modules only)
      • 2.4.2.3. Using PEG Pins for General Purpose PCIe Lanes
    • 2.4.3. Reference Schematics
      • 2.4.3.1. x1, x4, x8, x16 Slot
    • 2.4.4. Routing Considerations
      • 2.4.4.1. Polarity Inversion
      • 2.4.4.2. Lane Reversal
  • 2.5. Digital Display Interfaces
    • 2.5.1. DisplayPort / HDMI / DVI
      • 2.5.1.1. Signal Definitions
      • 2.5.1.2. Reference Schematic
        • DisplayPort Example
        • HDMI Example
        • DVI Example
        • Other DisplayPort Output Options: LVDS, VGA, etc.
      • 2.5.1.3. Routing Considerations
    • 2.5.2. SDVO
      • 2.5.2.1. Signal Definitions
        • SDVO Port Configuration
        • Supported SDVO Devices
      • 2.5.2.2. Reference Schematics
        • SDVO to DVI Transmitter Example
        • Other SDVO Output Options: LVDS, NTSC
      • 2.5.2.3. Routing Considerations
        • SDVO Option – PEG Lane Reversal
  • 2.6. Mobile PCI Express Module (MXM)
    • 2.6.1. Signal Definitions
    • 2.6.2. Reference Schematics
    • 2.6.3. Routing Considerations
  • 2.7. LAN
    • 2.7.1. Signal Definitions
      • 2.7.1.1. Status LED Signal Definitions
      • 2.7.1.2. LAN 1 and 2 shared with IDE
      • 2.7.1.3. PHY / Magnetics Connections
    • 2.7.2. Reference Schematics
      • 2.7.2.1. Magnetics Integrated Into RJ-45 Receptacle
      • 2.7.2.2. Discrete Coupling Transformer
    • 2.7.3. Routing Considerations
      • 2.7.3.1. Reference Ground Isolation and Coupling
  • 2.8. USB Ports
    • 2.8.1. Signal Definitions
      • 2.8.1.1. USB Over-Current Protection (USB_x_y_OC#)
      • 2.8.1.2. Powering USB devices during S5
      • 2.8.1.3. USB connector
    • 2.8.2. Reference Schematics
    • 2.8.3. Avoiding Back-driving Problems
    • 2.8.4. Routing Considerations
      • 2.8.4.1. EMI / ESD Protection
  • 2.9. USB 3.0
    • 2.9.1. Signal Definitions
      • 2.9.1.1. USB Differential lines (USB[0:3/1]+/-)
      • 2.9.1.2. USB Over-Current Protection (USB_x_y_OC#)
      • 2.9.1.3. USB 3.0 connector
    • 2.9.2. Reference Schematics
      • 2.9.2.1. USB 3.0 Example
    • 2.9.3. Avoiding Back-driving Problems
    • 2.9.4. Routing Considerations
      • 2.9.4.1. EMI / ESD Protection
  • 2.10. SATA
    • 2.10.1. Signal Definitions
    • 2.10.2. Reference Schematic
    • 2.10.3. Routing Considerations
  • 2.11. LVDS
    • 2.11.1. Signal Definitions
      • 2.11.1.1. Connector and Cable Considerations
      • 2.11.1.2. Display Timing Configuration
      • 2.11.1.3. Backlight Control
      • 2.11.1.4. Color Mapping and Terms
        • FPD-Link and Open LDI Color Mapping
      • 2.11.1.5. Note on Industry Terms
      • 2.11.1.6. LVDS Display Color Mapping Tables
    • 2.11.2. Reference Schematics
    • 2.11.3. Routing Considerations
  • 2.12. Embedded DisplayPort (eDP)
    • 2.12.1. Signal Definitions
    • 2.12.2. Reference Schematics
    • 2.12.3. Routing Considerations
  • 2.13. VGA
    • 2.13.1. Signal Definitions
    • 2.13.2. VGA Connector
    • 2.13.3. VGA Reference Schematics
    • 2.13.4. Routing Considerations
      • 2.13.4.1. RGB Analog Signals
      • 2.13.4.2. HSYNC and VSYNC Signals
      • 2.13.4.3. DDC Interface
      • 2.13.4.4. ESD Protection/EMI
  • 2.14. TV-Out
  • 2.15. Digital Audio Interfaces
    • 2.15.1. Reference Schematics
      • 2.15.1.1. High Definition Audio
      • 2.15.1.2. AC'97
      • 2.15.1.3. Routing Considerations
  • 2.16. LPC Bus – Low Pin Count Interface
    • 2.16.1. Signal Definition
    • 2.16.2. LPC Bus Reference Schematics
      • 2.16.2.1. LPC Bus Clock Signal
      • 2.16.2.2. LPC Reset Signal
      • 2.16.2.3. LPC PLD Example – Port 80 Decoder
      • 2.16.2.4. SuperIO
    • 2.16.3. Routing Considerations
      • 2.16.3.1. General Signals
      • 2.16.3.2. Bus Clock Routing
  • 2.17. SPI – Serial Peripheral Interface Bus
    • 2.17.1. Signal Definition
    • 2.17.2. SPI Reference Schematics
    • 2.17.3. Routing Considerations
  • 2.18. General Purpose I2C Bus Interface
    • 2.18.1. Signal Definitions
    • 2.18.2. Reference Schematics
    • 2.18.3. Connectivity Considerations
  • 2.19. System Management Bus (SMBus)
    • 2.19.1. Signal Definitions
    • 2.19.2. Routing Considerations
  • 2.20. General Purpose Serial Interface
    • 2.20.1. Signal Definitions
    • 2.20.2. Reference Schematics
      • 2.20.2.1. General Purpose Serial Port Example
    • 2.20.3. Routing Considerations
  • 2.21. CAN Interface
    • 2.21.1. Signal Definitions
    • 2.21.2. Reference Schematics
      • 2.21.2.1. CAN Bus Example
    • 2.21.3. Routing Considerations
  • 2.22. Miscellaneous Signals
    • 2.22.1. Module Type Detection
    • 2.22.2. Speaker Output
    • 2.22.3. RTC Battery Implementation
      • 2.22.3.1. RTC Battery Lifetime
    • 2.22.4. Power Management Signals
    • 2.22.5. Watchdog Timer
    • 2.22.6. General Purpose Input/Output (GPIO)
    • 2.22.7. SDIO Interface Multiplexed with GPIOs
    • 2.22.8. Fan Connector
    • 2.22.9. Thermal Interface
    • 2.22.10. Protecting COM.0 Pins Reclaimed From the VCC_12V Pool
      • 2.22.10.1. Logic Level Signals on Pins Reclaimed from VCC_12V
      • 2.22.10.2. TYPE10# Strap - Reclaimed from VCC_12V
  • 2.23. PCI Bus
    • 2.23.1. Signal Definitions
    • 2.23.2. Reference Schematics
      • 2.23.2.1. Resource Allocation
      • 2.23.2.2. Device-Down Example
      • 2.23.2.3. Device-Down Considerations
      • 2.23.2.4. Clock Buffer
    • 2.23.3. Routing Considerations
      • 2.23.3.1. General PCI Signals
      • 2.23.3.2. PCI Clock Routing
  • 2.24. IDE and CompactFlash (PATA)
    • 2.24.1. Signal Definitions
    • 2.24.2. IDE 40-Pin Header (3.5 Inch Drives)
    • 2.24.3. IDE 44-Pin Header (2.5 Inch and Low Profile Optical Drives)
    • 2.24.4. CompactFlash 50 Pin Header
    • 2.24.5. IDE / CompactFlash Reference Schematics
    • 2.24.6. Routing Considerations
• 3. Power and Reset
  • 3.1. General Power requirements
    • 3.1.1. VCC_12V Rise Time Caution and Inrush Currents
  • 3.2. ATX and AT Style Power Control
    • 3.2.1. ATX vs AT Supplies
    • 3.2.2. Power States
    • 3.2.3. ATX and AT Power Sequencing Diagrams
    • 3.2.4. Power Monitoring Circuit Discussion
    • 3.2.5. Power Button
  • 3.3. Design Considerations for Carrier Boards containing FPGAs/CPLDs
  • 3.4. Reference Schematics
    • 3.4.1. ATX Power Supply
      • 3.4.1.1. Minimum Loads
  • 3.5. Routing Considerations
    • 3.5.1. VCC_12V and GND
    • 3.5.2. Copper Trace Sizing and Current Capacity
    • 3.5.3. VCC5_SBY Routing
    • 3.5.4. Power State and Reset Signal Routing
    • 3.5.5. Slot Card Supply Decoupling Recommendations
• 4. BIOS Considerations
  • 4.1. Legacy versus Legacy-Free
  • 4.2. Super I/O
• 5. COM Express Module Connectors
  • 5.1. Connector Descriptions
  • 5.2. Connector Land Patterns and Alignment
  • 5.3. Connector and Module CAD Symbol Recommendations
• 6. Carrier Board PCB Layout Guidelines
  • 6.1. General
  • 6.2. PCB Stack-ups
    • 6.2.1. Four-Layer Stack-up
    • 6.2.2. Six-Layer Stack-up
    • 6.2.3. Eight-Layer Stack-up
  • 6.3. Trace-Impedance Considerations
  • 6.4. Trace-Length Extensions Considerations
  • 6.5. Routing Rules for High-Speed Differential Interfaces
    • 6.5.1. PCI Express Trace Routing Guidelines
    • 6.5.2. USB Trace Routing Guidelines
    • 6.5.3. USB 3.0 Trace Routing Guidelines
    • 6.5.4. PEG Trace Routing Guidelines
    • 6.5.5. SDVO Trace Routing Guidelines
    • 6.5.6. DisplayPort Trace Routing Guidelines
    • 6.5.7. LAN Trace Routing Guidelines
    • 6.5.8. Serial ATA Trace Routing Guidelines
    • 6.5.9. LVDS Trace Routing Guidelines
  • 6.6. Routing Rules for Single Ended Interfaces
    • 6.6.1. PCI Trace Routing Guidelines
    • 6.6.2. IDE Trace Routing Guidelines
    • 6.6.3. LPC Trace Routing Guidelines
• 7. Mechanical Considerations
  • 7.1. Form Factors
  • 7.2. Heatspreader
    • 7.2.1. Top mounting
    • 7.2.2. Bottom mounting
    • 7.2.3. Materials
• 8. Applicable Documents and Standards
  • 8.1. Technology Specifications
  • 8.2. Regulatory Specifications
  • 8.3. Useful books
• 9. Appendix A: Deprecated Features
  • 9.1. TV-Out
    • 9.1.1. Signal Definitions
    • 9.1.2. TV-Out Connector
    • 9.1.3. TV-Out Reference Schematics
    • 9.1.4. Routing Considerations
    • 9.1.5. Signal Termination
    • 9.1.6. Video Filter
    • 9.1.7. ESD Protection
  • 9.2. LPC Firmware Hub
• 10. Appendix B: Sourcecode for Port 80 Decoder
• 11. Appendix C: List of Tables
• 12. Appendix D: List of Figures
• 13. Appendix E: Revision History