17 power architecture, 1 block diagram discussion, Power architecture – Kontron SMARC Evaluation Carrier User Manual
Page 65: Block diagram discussion
User’s Guide
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17 Power Architecture
17.1 Block Diagram Discussion
A block diagram of the supply architecture used on the Evaluation Carrier is shown on the following page. Some points
about this diagram:
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As outlined in the SMARC specification document, there are separate Module and Carrier power domains.
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Some of the circuitry on the Evaluation Carrier is within the Module power domain (even those circuits are
physically on the Carrier). Such circuits include the power control circuit shown at the lower left of the block
diagram, and the I2C_PM based Carrier EEPROM (not shown in this diagram).
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Al Carrier I2C_PM devices are in the Module power domain (and are not shown in this diagram)
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The Evaluation Carrier implements a pair of power P-FETS that allow 1.8V or 3.3V Module I/O. If the Module ties
Module pin S158 (pin name VDD_IO_EL#) to GND, then the Module is selecting 1.8V I/O
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If the Evaluation Carrier is built with resistor R275 not loaded, the Evaluation Carrier power rails all come up
when there is input power available.
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If R275 is loaded with a low value resistor, then the Evaluation Carrier power rails that are in the Carrier power
domain do not come up until the Module asserts Module pin S154 high (Module pin name CARRIER_PWR_ON).
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A pair of I/O expanders is available on the I2C_PM bus that allows fine-grained control of the various Carrier
domain power supplies. By default, these I/O expanders are inactive, all of their I/O pins are inputs, and they
exert no control. They are described Section 15.3 I2C PM Bus I/O Expanders.