Panasonic KX-P1150 User Manual
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KX-P1150
(4) Gate Array
The gate array (IC205) is a 100 pin Flat Package, which consists of seven blocks.
(a) Head Drive Controller
The 9 Print Head Pins are controlled by a Head pin group controller. The Head Pin Trigger Pulse
triggers generation of the Head Pin Signal from each group.
(b) Decoder
It is used for accessing ROM and RAMs, and used for refreshing RAMs.
(c) Handshake Interface
In this gate array, the Centronics Parallel Interface (usually called Handshake Interface) is prepared.
The busy signal to the host computer is generated automatically when receiving the DSTB (data
strobe) signal. The ACK (acknowledge) signal is also generated automatically when the busy signal
turns to L level (Ready state).
(d) Pulse Generator for Stepper Motor
In this gate array the pulse generator for the stepper motor is prepared. This function is used for the
carriage spacing motor and line feed motor. The motor driving pattern is generated automatically
when the generator receives the starting signal. This pattern is synchronized with the output of the
timer which determines motor pulse rate.