15 microphone, 1 spi interface, 2 interrupts – Digilent 410-292P-KIT User Manual
Page 24
Nexys4 DDR™ FPGA Board Reference Manual
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Page 24 of 29
Artix 7
ADXL362
MISO
~CS
SCLK
E15
D15
F15
MOSI: Master Out Slave In
MISO: Master In Slave Out
~CS: Slave Select (Active Low)
F14
MOSI
SCLK: Serial Clock
INT2
INT1
C16
B13
INT1: Interrupt One
INT2: Interrupt Two
Figure 23. Accelerometer interface.
14.1 SPI Interface
The ADXL362 acts as a slave device using an SPI communication scheme. The recommended SPI clock frequency
ranges from 1 MHz to 5 MHz. The SPI operates in SPI mode 0 with CPOL = 0 and CPHA = 0. All communications with
the device must specify a register address and a flag that indicate whether the communication is a read or a write.
Actual data transfer always follows the register address and communication flag. Device configuration can be
performed by writing to the control registers within the accelerometer. Access accelerometer data by reading the
device registers.
For a full list of registers, their functionality, and communication specifications, refer to the ADXL362 datasheet
5
.
14.2 Interrupts
Several of the built-in functions of the ADXL362 can trigger interrupts that alert the host processor of certain status
conditions. Interrupts can be mapped to either (or both) of two interrupt pins (INT1, INT2). Both of these pins
require internal FPGA pull-ups when used. For more details about the interrupts, see the ADXL362 datasheet.
15 Microphone
The Nexys4 DDR board includes an omnidirectional MEMS microphone. The microphone uses an Analog Device
ADMP421 chip which has a high signal to noise ratio (SNR) of 61dBA and high sensitivity of -26 dBFS. It also has a
flat frequency response ranging from 100Hz to 15 kHz. The digitized audio is output in the pulse density modulated
(PDM) format. The component architecture is shown in Figure 24.
Artix 7
ADMP421
CLK
DATA
L/R SEL
J5
H5
F5
Microphone
CLK: Clock Input to Microphone
DATA: Data Output Signal
L/R SEL: Left/Right Channel Select
Figure 24. Microphone block diagram.