Cypress CY7C1354CV25 - Manual (Page 18)

CY7C1354CV25
CY7C1356CV25
Document #: 38-05537 Rev. *H Page 18 of 28
Switching Characteristics Over the Operating Range
[18, 19]
Parameter Description
–250 –200 –166
Unit Min. Max. Min. Max. Min. Max.
t
Power
[17] V
CC
(typical) to the First Access Read or Write 1 1 1 ms
Clock
t
CYC
Clock Cycle Time 4.0 5 6 ns
F
MAX
Maximum Operating Frequency 250 200 166 MHz
t
CH
Clock HIGH 1.8 2.0 2.4 ns
t
CL
Clock LOW 1.8 2.0 2.4 ns
Output Times
t
CO
Data Output Valid after CLK Rise 2.8 3.2 3.5 ns
t
EOV
OE LOW to Output Valid 2.8 3.2 3.5 ns
t
DOH
Data Output Hold after CLK Rise 1.25 1.5 1.5 ns
t
CHZ
Clock to High-Z
[20, 21, 22]
1.25 2.8 1.5 3.2 1.5 3.5 ns
t
CLZ
Clock to Low-Z
[20, 21, 22]
1.25 1.5 1.5 ns
t
EOHZ
OE HIGH to Output High-Z
[20, 21, 22]
2.8 3.2 3.5 ns
t
EOLZ
OE LOW to Output Low-Z
[20, 21, 22]
0 0 0 ns
Set-up Times
t
AS
Address Set-up before CLK Rise 1.4 1.5 1.5 ns
t
DS
Data Input Set-up before CLK Rise 1.4 1.5 1.5 ns
t
CENS
CEN Set-up before CLK Rise 1.4 1.5 1.5 ns
t
WES
WE, BW
x
Set-up before CLK Rise 1.4 1.5 1.5 ns
t
ALS
ADV/LD Set-up before CLK Rise 1.4 1.5 1.5 ns
t
CES
Chip Select Set-up 1.4 1.5 1.5 ns
Hold Times
t
AH
Address Hold after CLK Rise 0.4 0.5 0.5 ns
t
DH
Data Input Hold after CLK Rise 0.4 0.5 0.5 ns
t
CENH
CEN Hold after CLK Rise 0.4 0.5 0.5 ns
t
WEH
WE, BW
x
Hold after CLK Rise 0.4 0.5 0.5 ns
t
ALH
ADV/LD Hold after CLK Rise 0.4 0.5 0.5 ns
t
CEH
Chip Select Hold after CLK Rise 0.4 0.5 0.5 ns
Notes:
17. This part has a voltage regulator internally; t
power
is the time power needs to be supplied above V
DD
minimum initially, before a Read or Write operation can be
initiated.
18. Timing reference level is when V
DDQ
= 2.5V.
19. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
20. t
CHZ
, t
CLZ
, t
EOLZ
, and t
EOHZ
are specified with AC test conditions shown in (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
21. At any given voltage and temperature, t
EOHZ
is less than t
EOLZ
and t
CHZ
is less than t
CLZ
to eliminate bus contention between SRAMs when sharing the same
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve High-Z prior to Low-Z under the same system conditions.
22. This parameter is sampled and not 100% tested.
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