Maxim Integrated 78Q8430 Software Driver - Manual (Page 27)

UG_8430_004 78Q8430 Software Driver Development Guidelines
Rev. 1.0 27
STEP 7: Read all available new data from QUE 0.
The amount of new data in the QUE is the new frame size (Count field) from the RPSR value minus
the amount of data already read into the buffer. Append the new frame data to the buffer at the
correct location.
STEP 8: Examine the new Done bit in the RPSR value.
If the Done bit is not set, repeat the procedure starting at STEP 4. If the Done bit is set, the entire
jumbo frame has been loaded into the buffer.
5.2.2 Transmit Jumbo
Use the following procedure to transmit jumbo frames that are too large to fit into the transmit QUE all at
once:
STEP 1: Write to the QUE 4 PCWR.
This initializes the write logic for QUE 4 and set the ID and transmission options for the frame. The
software should assign a unique ID number to each transmitted frame. Initializing the write logic
triggers an under-run interrupt for QUE 4 if the previous frame transmission is not complete. This has
the effect of aborting the previous frame.
STEP 2: Write the QUE 4 PSZR Packet Size field.
This indicates to the QUE 4 write logic how many bytes to expect. For example, if the part is
operating in 32-bit bus mode and the byte count is not an even multiple of four the write logic uses the
Packet Size value to determine how many bytes in the last write are valid. An overrun interrupt
results if the host attempts to write an extra word past the end of the programmed size.
STEP 3: Set the QSR Threshold and Mode fields for QUE 4.
Set the QSR Mode field to 3 and the Threshold field to 5. With these settings, anytime the amount of
data in the QUE is 1024 bytes or less, the Below Condition will be true.
STEP 4: Enable the B Rise interrupt for QUE 4.
Set the QSMR bit corresponding to the QUE 4 B Rise interrupt to enable the interrupt.
STEP 5: Enable the QSIR interrupt.
Set the HIMR Que Status bit to enable the QSIR interrupt.
STEP 6: Write the first 2048 bytes of the frame to the QUE 4 TDR.
Now that the QUE contains data the Below Condition should be clear.
STEP 7: Read QSIR.
This clears the B Rise interrupt that was set when the QUE was empty.
STEP 8: Wait for a QSIR interrupt.
The interrupt occurs when the MAC transmitter has removed data from the transmit QUE such that it
is below the threshold set in STEP 1.
STEP 9: Write an additional 2048 bytes of the frame to the QUE 4 TDR.
STEP 10: Clear the QSIR interrupt by reading QSIR.
The QSIR is clear-on-read.
STEP 11: Repeat STEP 8 through STEP 10 until the entire frame is written to the QUE 4 TDR.
The final amount of data written in STEP 9 will likely be less than 2048 bytes.
STEP 12: Clear the QSMR so that the QSIR interrupts will no longer be received.
Now that the final bytes of the frame are in the QUE, the MAC transmitter is free to empty it without
any more involvement of the driver.