Maxim Integrated 78Q8430 Software Driver - Manual (Page 37)

UG_8430_004 78Q8430 Software Driver Development Guidelines
Rev. 1.0 37
6 Counter Rollover Monitor (RMON)
The 78Q8430 includes a block of hardware counters to monitor transmit and receive statistics. All
hardware statistics counters are 32-bits. Since the driver is required to maintain 64-bit statistics counts, it
is responsible for maintaining the upper 32 bits of each 64-bit counter. Rollover interrupt hardware that
can be individually enabled or disabled for each counter is provided to assist the driver to implement this.
Refer to the “Counters” section in the 78Q8430 Data Sheet for additional information on the statistics
counters and RMON interrupts. The following sections describe how to use the RMON feature.
6.1 Read Counters
Use the following procedure to read the statistics counter value:
STEP 1: Configure the CCR for the counter to be read.
• Fill the CCR Address field with the address of the counter to be read.
• Clear the Access Mode bit to specify read mode.
• Make sure the Clear on Read bit is clear (if this bit is set, the counter is automatically cleared
when it is read).
• The CCR Auto Increment bit should always be set.
STEP 2: Read CDR to retrieve the counter value.
The CCR Address field is automatically incremented after each read or write access to the CDR. This
allows many counters to be accessed through repeated reads or writes of the CDR without reconfiguring
the CCR.
6.2 Clear all Counters
Use the following procedure to instantaneously clear all the hardware statistics counters to zero at exactly
the same time:
STEP 1: Set the CMR Clear Receive and Clear Transmit bits.
No further action is necessary.
6.3 RMON Interrupts
The RMON interrupts are the best way to maintain the upper 32 bits of a 64 bit count (rollover count).
Each transmit and receive statistics counter has a corresponding rollover bit which can be individually
enabled to trigger a host interrupt each time the corresponding hardware 32-bit counter rolls over. Use
the following procedure to implement the RMON interrupts:
STEP 1: Enable the rollover interrupts.
Set the TRMR and RRMR bits corresponding to the transmit and receive statistics counters to be
monitored for rollover. Set the HIMR RMON bit.
TRMR bits 0 through 14 correspond to transmit counters 0 through 14. RRMR bits 0 through 24
correspond to receive counters 15 through 39.
STEP 2: Wait for an RMON interrupt.
The HIR RMON bit will be set to indicate an RMON interrupt has occurred.
STEP 3: Read TRIR.
A single bit will be set in TRIR for each transmit counter that has rolled over. The driver increments
by one each rollover counter that corresponds to a TRIR set bit.