Document Outline

• TABLE OF CONTENTS:
• SECTION 1: OVERVIEW
  • 1.1 Instruction Set
  • 1.2 Harvard Memory Architecture
  • 1.3 Register Set
  • 1.4 MAXQ10 and MAXQ20 Microc...
• SECTION 2: ARCHITECTURE
  • 2.1 Instruction Decoding
  • 2.2 Register Space
  • 2.3 Memory Organization
    • 2.3.1 Program Memory
    • 2.3.2 Utility ROM
    • 2.3.3 Data Memory
    • 2.3.4 Stack Memory
  • 2.4 Pseudo-Von Neumann Memor...
  • 2.5 Pseudo-Von Neumann Memor...
  • 2.6 Data Alignment
    • 2.6.1 Memory Management Unit
  • 2.7 Clock Generation
    • 2.7.1 Internal Ring Oscillator
    • 2.7.2 External Clock (Crysta...
    • 2.7.3 External Clock (Direct...
    • 2.7.4 External RC
    • 2.7.5 Internal System Clock ...
  • 2.8 Interrupts
    • 2.8.1 Servicing Interrupts
    • 2.8.2 Interrupt System Opera...
    • 2.8.3 Synchronous vs. Asynch...
    • 2.8.4 Interrupt Prioritizati...
    • 2.8.5 Interrupt Exception Wi...
  • 2.9 Operating Modes
    • 2.9.1 Reset Mode
      • 2.9.1.1 Power-On/Brownout Reset
      • 2.9.1.2 External Reset
      • 2.9.1.3 Watchdog Timer Reset
      • 2.9.1.4 Internal System Reset
    • 2.9.2 Power Management Mode
      • 2.9.2.1 Switchback
    • 2.9.3 Stop Mode
• SECTION 3: PROGRAMMING
  • 3.1 Addressing Modes
  • 3.2 Prefixing Operations
  • 3.3 Reading and Writing Regi...
    • 3.3.1 Loading an 8-Bit Regis...
    • 3.3.2 Loading a 16-Bit Regis...
    • 3.3.3 Moving Values Between ...
    • 3.3.4 Moving Values Between ...
  • 3.4 Reading and Writing Regi...
  • 3.5 Using the Arithmetic and...
    • 3.5.1 Selecting the Active A...
    • 3.5.2 Enabling Auto-Incremen...
    • 3.5.3 ALU Operations Using t...
    • 3.5.4 ALU Operations Using O...
    • 3.5.5 ALU Bit Operations Usi...
    • 3.5.6 MAXQ10 Example: Adding...
    • 3.5.7 MAXQ20 Example: Adding...
  • 3.6 Processor Status Flag Op...
    • 3.6.1 Sign Flag
    • 3.6.2 Zero Flag
    • 3.6.3 Equals Flag
    • 3.6.4 Carry Flag
    • 3.6.5 Overflow Flag
  • 3.7 Controlling Program Flow
    • 3.7.1 Obtaining the Next Exe...
    • 3.7.2 Unconditional Jumps
    • 3.7.3 Conditional Jumps
    • 3.7.4 Calling Subroutines
    • 3.7.5 Looping Operations
    • 3.7.6 Conditional Returns
  • 3.8 Handling Interrupts
    • 3.8.1 Conditional Return fro...
  • 3.9 Accessing the Stack
  • 3.10 Accessing Data Memory
  • 3.11 Using the Watchdog Timer
• SECTION 4: SYSTEM REGISTER DESCRIPTIONS
  • 4.1 Accumulator Pointer Regi...
  • 4.2 Accumulator Pointer Cont...
  • 4.3 Processor Status Flags R...
  • 4.4 Interrupt and Control Re...
  • 4.5 Interrupt Mask Register ...
  • 4.6 System Control Register ...
  • 4.7 Interrupt Identification...
  • 4.8 System Clock Control Reg...
  • 4.9 Watchdog Control Registe...
  • 4.10 (MAXQ10) Accumulator n ...
  • 4.11 (MAXQ20) Accumulator n ...
  • 4.12 Prefix Register (PFX[n]...
  • 4.13 Instruction Pointer Reg...
  • 4.14 Stack Pointer Register ...
  • 4.15 Interrupt Vector Regist...
  • 4.16 Loop Counter 0 Register...
  • 4.17 Loop Counter 1 Register...
  • 4.18 Frame Pointer Offset Re...
  • 4.19 Data Pointer Control Re...
  • 4.20 General Register (GR, E...
  • 4.21 General Register Low By...
  • 4.22 Frame Pointer Base Regi...
  • 4.23 General Register Byte-S...
  • 4.24 General Register High B...
  • 4.25 General Register Sign E...
  • 4.26 Frame Pointer Register ...
  • 4.27 Data Pointer 0 Register...
  • 4.28 Data Pointer 1 Register...
• SECTION 5: PERIPHERAL REGISTER MODULES
• SECTION 6: GENERAL-PURPOSE I/O MODULE
  • 6.1 I/O Port: Type A
  • 6.2 I/O Port: Type B
  • 6.3 I/O Port: Type C
  • 6.4 I/O Port: Type D
  • 6.5 I/O Port Peripheral Regi...
    • 6.5.1 Port Output x Register...
    • 6.5.2 Port Input x Register ...
    • 6.5.3 Port Direction x Regis...
    • 6.5.4 (Type A) External Inte...
    • 6.5.5 (Type A) External Inte...
    • 6.5.6 (Type D) External Inte...
    • 6.5.7 (Type D) External Inte...
    • 6.5.8 (Type D) External Inte...
• SECTION 7: TIMER/COUNTER 0 MODULE
  • 7.1 Timer 0
    • 7.1.1 Timer 0 Mode: 13-Bit T...
    • 7.1.2 Timer 0 Mode: 16-Bit T...
    • 7.1.3 Timer 0 Mode: 8-Bit Ti...
    • 7.1.4 Timer 0 Mode: Two 8-Bi...
  • 7.2 Timer/Counter 0 Peripher...
    • 7.2.1 Timer/Counter 0 Contro...
    • 7.2.2 Timer/Counter 0 High R...
    • 7.2.3 Timer/Counter 0 Low Re...
• SECTION 8: TIMER/COUNTER 1 MODULE
  • 8.1 Timer 1
    • 8.1.1 Timer 1 Mode: 16-Bit T...
    • 8.1.2 Timer 1 Mode: 16-Bit E...
    • 8.1.3 Timer 1 Mode: Up/Down ...
    • 8.1.4 Timer 1 Mode: Clock Ou...
  • 8.2 Timer/Counter 1 Peripher...
    • 8.2.1 Timer/Counter 1 Contro...
    • 8.2.2 Timer/Counter 1 High R...
    • 8.2.3 Timer/Counter 1 Low Re...
    • 8.2.4 Timer/Counter 1 High R...
    • 8.2.5 Timer/Counter 1 Low Re...
    • 8.2.6 Timer/Counter 1 Mode R...
  • 8.3 Time-Base Selection for ...
• SECTION 9: TIMER/COUNTER 2 MODULE
  • 9.1 Timer 2
  • 9.2 Modes of Operation
    • 9.2.1 16-Bit Timer: Auto-Rel...
      • 9.2.1.1 Output Enable (PWM Out)
      • 9.2.1.2 Polarity Control
      • 9.2.1.3 Gated
      • 9.2.1.4 Single Shot (and Gat...
      • 9.2.1.5 Capture/Reload Control
    • 9.2.2 16-Bit Timer: Capture ...
      • 9.2.2.1 Output Enables
      • 9.2.2.2 Polarity Control
      • 9.2.2.3 Edge Detection
      • 9.2.2.4 Gated
      • 9.2.2.5 Single Shot
      • 9.2.2.6 Capture and Reload
    • 9.2.3 16-Bit Counter
      • 9.2.3.1 Output Enable
      • 9.2.3.2 Polarity Control
      • 9.2.3.3 Gating and Single Shot
    • 9.2.4 Dual 8-Bit Timers
      • 9.2.4.1 Output Enable (PWM Out)
      • 9.2.4.2 Polarity Control
      • 9.2.4.3 Gated
      • 9.2.4.4 Single Shot
    • 9.2.5 8-Bit Timer/8-Bit Capt...
    • 9.2.6 8-Bit Timer/8-Bit Counter
    • 9.2.7 Timer 2 Input Clock Se...
  • 9.3 Timer 2 Capture Applicat...
    • 9.3.1 Measure Low-Pulse Dura...
    • 9.3.2 Measure High-Pulse Dur...
    • 9.3.3 Measure Period
    • 9.3.4 Measure Duty Cycle Rep...
    • 9.3.5 Overflow/Interrupt on ...
  • 9.4 Timer/Counter 2 Peripher...
    • 9.4.1 Timer/Counter 2 Config...
    • 9.4.2 Timer/Counter 2 Contro...
    • 9.4.3 Timer/Counter 2 Contro...
    • 9.4.4 Timer 2 Value Register...
    • 9.4.5 Timer 2 Value High Reg...
    • 9.4.6 Timer 2 Reload Registe...
    • 9.4.7 Timer 2 Reload High Re...
    • 9.4.8 Timer 2 Capture/Compar...
    • 9.4.9 Timer 2 Capture/Compar...
  • 9.5 Low-Speed Infrared Trans...
    • 9.5.1 Subcarrier Generation ...
    • 9.5.2 Transmit Baseband Modu...
      • 9.5.2.1 IR Encoding (Transmi...
      • 9.5.2.2 Receive Pin Sampling
      • 9.5.2.3 IR Decoding (Receive...
  • 9.6 IR Peripheral Register
    • 9.6.1 Infrared Control Regis...
• SECTION 10: SERIAL I/O MODULE
  • 10.1 UART Modes
    • 10.1.1 UART Mode 0
    • 10.1.2 UART Mode 1
    • 10.1.3 UART Mode 2
    • 10.1.4 UART Mode 3
  • 10.2 Baud-Rate Generation
    • 10.2.1 Mode 0 Baud Rate
    • 10.2.2 Mode 2 Baud Rate
    • 10.2.3 Mode 1 or 3 Baud Rate
    • 10.2.4 Baud-Clock Generator
  • 10.3 Framing Error Detection
  • 10.4 UART Peripheral Registers
    • 10.4.1 Serial Control Regist...
    • 10.4.2 Serial Port Mode Regi...
    • 10.4.3 Serial Port Data Buff...
    • 10.4.4 Serial Port Phase Reg...
• SECTION 11: SERIAL PERIPHERAL INTERFACE (SPI) MODULE
  • 11.1 SPI Transfer Formats
  • 11.2 SPI Character Lengths
  • 11.3 SPI Transfer Baud Rates
  • 11.4 SPI System Errors
    • 11.4.1 Mode Fault
    • 11.4.2 Receive Overrun
    • 11.4.3 Write Collision While...
  • 11.5 SPI Master Operation
  • 11.6 SPI Slave Operation
  • 11.7 SPI Peripheral Registers
    • 11.7.1 SPI Control Register ...
    • 11.7.2 SPI Configuration Reg...
    • 11.7.3 SPI Clock Register (S...
    • 11.7.4 SPI Data Buffer Regis...
• SECTION 12: HARDWARE MULTIPLIER MODULE
  • 12.1 Hardware Multiplier Org...
  • 12.2 Hardware Multiplier Con...
  • 12.3 Register Output Selection
    • 12.3.1 Signed-Unsigned Opera...
    • 12.3.2 Operand Count Selection
  • 12.4 Hardware Multiplier Ope...
    • 12.4.1 Accessing the Multipl...
  • 12.5 Hardware Multiplier Per...
    • 12.5.1 Hardware Multiplier C...
    • 12.5.2 Multiplier Operand A ...
    • 12.5.3 Multiplier Operand B ...
    • 12.5.4 Multiplier Accumulato...
    • 12.5.5 Multiplier Accumulato...
    • 12.5.6 Multiplier Accumulato...
    • 12.5.7 Multiplier Read Regis...
    • 12.5.8 Multiplier Read Regis...
  • 12.6 Hardware Multiplier Exa...
• SECTION 13: 1-Wire BUS MASTER
  • 13.1 1-Wire Peripheral Regis...
    • 13.1.1 1-Wire Address Regist...
    • 13.1.2 1-Wire Data Register ...
  • 13.2 1-Wire Clock Control
    • 13.2.1 1-Wire Clock Divisor ...
  • 13.3 1-Wire Bus Master Control
    • 13.3.1 1-Wire Control Regist...
  • 13.4 1-Wire Bus Master Comma...
    • 13.4.1 1-Wire Command Regist...
  • 13.5 Search Operation Using ...
    • 13.5.1 Accelerated ROM Searc...
  • 13.6 1-Wire Transmit and Rec...
    • 13.6.1 1-Wire Transmit/Recei...
  • 13.7 1-Wire Bus Master Inter...
    • 13.7.1 1-Wire Interrupt Flag...
    • 13.7.2 1-Wire Interrupt Enab...
  • 13.8 I/O Signaling
• SECTION 14: REAL-TIME CLOCK MODULE
  • 14.1 RTC Alarm Functions
    • 14.1.1 Time-of-Day Alarm
    • 14.1.2 Sub-Second Alarm
    • 14.1.3 System Wakeup by Time...
  • 14.2 RTC Trim Function
  • 14.3 RTC Register Access
    • 14.3.1 Busy Bit Write Signaling
    • 14.3.2 Ready Bit Read Signaling
    • 14.3.3 RTC Count Register Ac...
    • 14.3.4 RTC Alarm Register Ac...
    • 14.3.5 RTC Trim Register Access
  • 14.4 RTC Peripheral Registers
    • 14.4.1 RTC Control Register ...
    • 14.4.2 RTC Seconds High Regi...
    • 14.4.3 RTC Seconds Low Regis...
    • 14.4.4 RTC Sub-Seconds Regis...
    • 14.4.5 RTC Alarm Seconds Hig...
    • 14.4.6 RTC Alarm Seconds Low...
    • 14.4.7 RTC Sub-Second Alarm ...
    • 14.4.8 RTC Trim Register (RTRM)
• SECTION 15: TEST ACCESS PORT (TAP)
  • 15.1 TAP Controller
  • 15.2 TAP State Control
    • 15.2.1 Test-Logic-Reset
    • 15.2.2 Run-Test-Idle
    • 15.2.3 IR-Scan Sequence
    • 15.2.4 DR-Scan Sequence
  • 15.3 Communication via TAP
    • 15.3.1 TAP Communication Exa...
• SECTION 16: IN-CIRCUIT DEBUG MODE
  • 16.1 Background Mode Operation
    • 16.1.1 Breakpoint Registers
      • 16.1.1.1 Breakpoint 0 Regist...
      • 16.1.1.2 Breakpoint 1 Regist...
      • 16.1.1.3 Breakpoint 2 Regist...
      • 16.1.1.4 Breakpoint 3 Regist...
      • 16.1.1.5 Breakpoint 4 Regist...
      • 16.1.1.6 Breakpoint 4 Regist...
      • 16.1.1.7 Breakpoint 5 Regist...
      • 16.1.1.8 Breakpoint 5 Regist...
    • 16.1.2 Using Breakpoints
  • 16.2 Debug Mode
    • 16.2.1 Debug Mode Commands
    • 16.2.2 Read Register Map Com...
    • 16.2.3 Single-Step Operation...
    • 16.2.4 Return
    • 16.2.5 Debug Mode Special Co...
  • 16.3 In-Circuit Debug Periph...
    • 16.3.1 In Circuit Debug Temp...
    • 16.3.2 In Circuit Debug Temp...
    • 16.3.3 In-Circuit Debug Cont...
    • 16.3.4 In-Circuit Debug Flag...
    • 16.3.5 In-Circuit Debug Buff...
    • 16.3.6 In Circuit Debug Data...
    • 16.3.7 In Circuit Debug Addr...
• SECTION 17: IN-SYSTEM PROGRAMMING (JTAG)
  • 17.1 JTAG Bootloader Operation
  • 17.2 Password-Protected Access
    • 17.2.1 Entering Password
• SECTION 18: MAXQ FAMILY INSTRUCTION SET SUMMARY
  • ADD/ADDC src
  • AND src
  • AND Acc.<b>
  • {L/S}CALL src
  • CMP src
  • CPL
  • CPL C
  • {L/S}DJNZ LC[n], src
  • {L/S} JUMP src
  • {L/S}JUMP C/{L/S}JUMP NC, sr...
  • MOVE dst, src
  • MOVE Acc.<b>, C
  • MOVE C, Acc.<b>
  • MOVE C, src.<b>
  • MOVE C, #0
  • MOVE C, #1
  • MOVE dst.<b>, #0
  • MOVE dst.<b>, #1
  • NEG
  • OR src
  • OR Acc.<b>
  • POP dst
  • POPI dst
  • PUSH src
  • RET
  • RET C/RET NC, RET Z/RET NZ, ...
  • RETI
  • RETI C/RETI NC, RETI Z/RETI ...
  • RL/RLC
  • RR/RRC
  • SLA/SLA2/SLA4
  • SR/SRA/SRA2/SRA4
  • SUB/SUBB src
  • XCH
  • XCHN
  • XOR src
  • XOR Acc.<b>
• REVISION HISTORY