Table 6. system register reset values, Maxq family user’s guide: maxq2000 supplement – Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement User Manual
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Table 6. System Register Reset Values
MAXQ Family User’s Guide:
MAXQ2000 Supplement
REG
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11
BIT 10
BIT 9
BIT 8
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
AP
0
0
0
0
0
0
0
0
APC
0
0
0
0
0
0
0
0
PSF
1
0
0
0
0
0
0
0
IC
0
0
0
0
0
0
0
0
IMR
0
0
0
0
0
0
0
0
SC
0
0
0
0
0
0
s
0
IIR
0
0
0
0
0
0
0
0
CKCN
0
s
s
0
0
0
0
0
WDCN
s
s
0
0
0
s
s
0
A[0..15]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PFX
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
IP
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SP
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
IV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LC[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Offs
0
0
0
0
0
0
0
0
DPC
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
GR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRL
0
0
0
0
0
0
0
0
BP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GRH
0
0
0
0
0
0
0
0
GRXL
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FP
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DP[1]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Note: Bits marked as “s” have special behavior upon reset; see register descriptions for details.
Maxim Integrated
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