Maxim Integrated MAXQ Family Users Guide: MAXQ2000 Supplement - Manual (Page 32)

MAXQ Family User’s Guide:
MAXQ2000 Supplement
REG BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
T2RH0 0 0 0 0 0 0 0 0
T2CH0 0 0 0 0 0 0 0 0
SPIB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCON1 0 0 0 0 0 0 0 0
SBUF1 0 0 0 0 0 0 0 0
SMD1 0 0 0 0 0 0 0 0
PR1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2CNB0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2V0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2C0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2CFG0 0 0 0 0 0 0 0 0
OWA 0 0 0 0 0 0 0 0
OWD 0 0 0 0 0 0 0 0
SPICN 0 0 0 0 0 0 0 0
SPICF 0 0 0 0 0 0 0 0
SPICK 0 0 0 0 0 0 0 0
ICDF s s s s s s s s
T2CNA1 0 0 0 0 0 0 0 0
T2H1 0 0 0 0 0 0 0 0
T2RH1 0 0 0 0 0 0 0 0
T2CH1 0 0 0 0 0 0 0 0
T2CNA2 0 0 0 0 0 0 0 0
T2H2 0 0 0 0 0 0 0 0
T2RH2 0 0 0 0 0 0 0 0
T2CH2 0 0 0 0 0 0 0 0
T2CNB1 0 0 0 0 0 0 0 0
T2V1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2R1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2C1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2CNB2 0 0 0 0 0 0 0 0
T2V2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2R2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2C2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
T2CFG1 0 0 0 0 0 0 0 0
T2CFG2 0 0 0 0 0 0 0 0
Table 9. Peripheral Register Bit Reset Values (continued)
Note: Bits marked as “s” have special behavior upon reset. See the register descriptions for details.
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