ADLINK PCI-9846 - Manual (Page 42)

32 Operation Theory
external timebase from the front panel connector (CLK IN), PXI
STAR or one of the PXI Trigger Bus lines.
You can supply the timebase from external SMB connector CLK
IN, which should be a sine wave or square wave signal. This sig-
nal is AC coupled with 50 Ω input impedance and the valid input
level is from 1 to 2 volts peak-to-peak. Note that the external clock
must be continuous for correct ADC operation because of the
pipeline architecture of the ADC.
3.3.3 External Clock from PXI Interfaces
The PCI/PXI-9816/26/46 can receive timebase via one of the PXI
Trigger Bus lines by software selection. The eight PXI Trigger Bus
lines (PXI_TRIG[0..7]) provide inter-module synchronization and
communication. Note that this function is only available when the
PCI/PXI-9816/26/46 is in a PXI system. It’s not supported when
PCI/PXI-9816/26/46 is in a CompactPCI system.
When the PCI/PXI-9816/26/46 is plugged into a generic peripheral
slot in a PXI system, it can receive timebase from PXI_STAR. The
PXI_STAR signal comes from star trigger controller is matched in
propagation delay within 1 ns and the delay from star trigger slot to
peripheral slot is less than 5 ns. According these hardware fea-
tures, the PCI/PXI-9816/26/46 can achieve very good synchroni-
zation performance when using PXI_STAR as timebase clock
source. Note that the function is only available when the PCI/PXI-
98x6 is in a PXI system. It’s not supported when the PCI/PXI-
9816/26/46 is in a CompactPCI system.
3.3.4 Sampling Rate Control
By specifying different scan interval counter (24-bit) value, differ-
ent sampling rate can be achieved. The following formula deter-
mines the ADC sampling rate.
Sampling Rate = TIMEBASE / ScanIntrv
Where ScanIntrv is scan interval counter, value can be 1, 2, 3, 4…
2
24
- 1.