ADLINK PCI-7300A User Manual
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Table of contents
Document Outline
- Table of Contents
- List of Tables
- List of Figures
- 1 Introduction
- 2 Installation
- 3 Registers
- 3.1 I/O Port Base Address
- 3.2 DI_CSR: DI Control & Status Register
- 3.3 DO_CSR: DO Control & Status Register
- 3.4 Auxiliary Digital I/O Register
- 3.5 INT_CSR: Interrupt Control and Status Register
- 3.6 DI_FIFO: DI FIFO direct access port
- 3.7 DO_FIFO: DO external data FIFO direct access port
- 3.8 FIFO_CR: FIFO almost empty/full register
- 3.9 POL_CNTRL: Control Signal Polarity Control Register
- 3.10 PLX PCI-9080 DMA Control Registers
- 4 Operation Theory
- 5 C/C++ Libraries
- 5.1 Libraries Installation
- 5.2 Programming Guide
- 5.3 _7300_Initial
- 5.4 _7300_Close
- 5.5 _7300_Configure
- 5.6 _7300_DI_Mode
- 5.7 _7300_DO_Mode
- 5.8 _7300_AUX_DI
- 5.9 _7300_AUX_DI_Channel
- 5.10 _7300_AUX_DO
- 5.11 _7300_AUX_DO_Channel
- 5.12 _7300_Alloc_DMA_Mem
- 5.13 _7300_Free_DMA_Mem
- 5.14 _7300_DI_DMA_Start
- 5.15 _7300_DI_DMA_Status
- 5.16 _7300_DI_DMA_Abort
- 5.17 _7300_GetOverrunStatus
- 5.18 _7300_DO_DMA_Start
- 5.19 _7300_DO_DMA_Status
- 5.20 _7300_DO_DMA_Abort
- 5.21 _7300_DO_PG_Start
- 5.22 _7300_DO_PG_Stop
- 5.23 _7300_DI_Timer
- 5.24 _7300_DO_Timer
- 5.25 _7300_Int_Timer
- 5.26 _7300_Get_Sample
- 5.27 _7300_Set_Sample
- 5.28 _7300_GetUnderrunStatus
- Appendix
- Warranty Policy