ADLINK PCI-7300A - Manual (Page 55)

Operation Theory 43
than the on-board FIFO buffer time. The FIFO size is 16K
sample, so it has 1.6 ms buffer time for 10MHz sampling rate
if the FIFO is empty when last DMA is complete. Users may
try different DMA buffer size to see how the DMA buffer size
affects the overall performance. Generally, the larger DMA
size the less overhead, however, the process time required
between DMAs also increases.
Digital Input DMA in External Clock Mode
The digital input data transfer can be controlled by external strobe,
which is from pin-83 DI-REQ of CN1. The operation sequence is
very similar to Internal Clock. The only difference is the clock
source comes from the outside peripheral devices. The operations
sequence of digital input with external clock are listed:
1. Define the input configuration to be 32-bit, 16-bit or 8-bit
data width.
2. Enable or disable the active terminators.
3. Define the input sampling rate as external clock. Con-
nect the external clock to the input pin DI-REQ.
4. Define the starting mode to be NoWait or WaitTRIG.
5. The digital input data are stored in the input FIFO after a
DI command is issued and waiting for DI-TRIG signal if
in WaitTRIG mode..
6. The data saved in FIFO will transfer to system memory
of your computer directly and automatically by bus mas-
tering DMA.
7. The DI-ACK signal indicates the status of the cPCI/PCI-
7300A’s input FIFO is in external clock mode. When the
digital input circuit of cPCI/PCI-7300A is enabled and its
FIFO is not almost full, the DIACK signal will remain
asserted. If the external device does not transfer data
according to the status of DI-ACK, the on-board FIFO
could be full and data could be lost.