ADLINK LPCI-3488A - Manual (Page 32)

24 Operation Theory
3.2 ADLINK GPIB Interface Cards Block Diagram
ADLINK’s LPCI-3488A and PXI-3488A GPIB interface cards
include a 2 KB FIFIO inside the FPGA IP to maximize data trans-
fer rates. Its state-of-the-art state machine in the the CPLD coordi-
nates the data flow between the PCI controller, FIFO and GPIB
bus.
Figure 3-2: Block Diagram of ADLINK GPIB Interface Cards
The FIFO can buffer data from the master (either from the PCI
controller or external device) when the target is busy. Efficiency is
thus significantly improved when transferring large blocks of data.
FPGA
GPIB IP
(Built-in 2 KB FIFO)
PCI
Controller
Bus
Transceiver/
Receiver
CPLD