Avalue EEV-EX03 - Manual (Page 30)

EEV-EX03
30 EEV-EX03 Quick Installation Guide
MEMR#
MEMR# instructs memory devices to drive data onto the data bus. MEMR# is
active for all memory read cycles.
SMEMR#
SMEMR# instructs memory devices to drive data onto the data bus. SMEMR# is
active for memory read cycles to addresses below 1MB.
MEMW#
MEMW# instructs memory devices to store the data present on the data bus.
MEMW# is active for all memory write cycles.
SMEMW#
SMEMW# instructs memory devices to store the data present on the data bus.
SMEMW# is active for all memory write cycles to address below 1MB.
IOR#
I/O read instructs an I/O device to drive its data onto the data bus. It may be driven
by the CPU or by the DMA controller. IOR# is inactive (high) during refresh cycles.
IOW#
I/O write instructs an I/O device to store the data present on the data bus. It may be
driven by the CPU or by the DMA controller. IOW# is inactive (high) during refresh
cycles.
IOCHK#
IOCHK# is an active-low input signal that indicates that an error has occurred on
the module bus. If I/O checking is enabled on the CPU module, an IOCHK#
assertion by a peripheral device sends a NMI to the processor.
IOCHRDY
The I/O Channel Ready is pulled low in order to extend the read or write cycles of
any bus access when required. The CPU, DMA controllers or refresh controller can
initiate the cycle.
Any peripheral that cannot present read data or strobe in write data within this
amount of time use IOCHRDY to extend these cycles.
This signal should not be held low for more than 2.5 µs for normal operation. Any
extension to more than 2.5 µs does not guarantee proper DRAM memory content
due to the fact that memory refresh is disabled while IOCHRDY is low.
M16#
The M16# signal determines when a 16-bit to 8-bit conversion is needed for
memory bus cycles. A conversion is done any time the CPU module requests a
16-bit memory cycle while the M16# line is high. If M16# is high, 16-bit CPU cycles
are automatically converted on the bus into two 8-bit cycles. If M16# is low, an
access to peripherals is done 16 bits wide.
IO16#
The IO16# signal determines when a 16-bit to 8-bit conversion is needed for I/O
bus cycles. A conversion is done any time the CPU module requests a 16-bit I/O
cycle while the IO16# line is high. If IO16# is high, 16-bit CPU cycles are
automatically converted on the bus into two 8-bit cycles. If IO16# is low, an access
to peripherals is done at 16 bit width.
REFSH#
REFSH# is pulled low whenever a refresh cycle is initiated. A refresh cycle is
activated every 15.6 us in order to prevent loss of DRAM data.
NOWS#
The Zero wait state signal tells the CPU to complete the current bus cycle without
inserting the default wait states. By default the CPU inserts 4 wait states for 8-bit
transfers and 1 wait state for 16-bit transfers.
MASTER#
This signal is used with a DRQ line to gain control of the system bus. A processor
or a DMA controller on the I/O channel may issue a DRQ to a DMA channel in
cascade mode and receive a DACK#. Upon receiving the DACK#, a bus master
may pull MASTER# low, which will allow it to control the system address, data and
control lines. After MASTER# is low, the bus master must wait one system clock
period before driving the address and data lines, and two clock periods before
issuing a read or write command. If this signal is held low for more than 15 us,
system memory may be lost as memory refresh is disabled during this process.
SYSCLK
SYSCLK is supplied by the CPU module and has a nominal frequency of about 8
MHz with a duty cycle of 40-60 percent. The frequency supplied by different CPU
modules may vary. This signal is supplied at all times except when the CPU
module is in sleep mode.
OSC
OSC is supplied by the CPU module. It has a nominal frequency of 14.31818 MHz
and a duty cycle of 40-60 percent. This signal is supplied at all times except when
the CPU module is in sleep mode.
RESETDRV
This active-high output is system reset generated from CPU modules. It is
responsible for resetting external devices.
DREQ
[0, 1, 2, 3, 5, 6, 7]
The asynchronous DMA request inputs are used by external devices to indicate
when they need service from the CPU modules DAM controllers. DREQ0..3 are
used for transfers between 8-bit I/O adapters and system memory. DREQ5..7 are
used for transfers between 16-bit I/O adapters and system memory. DRQ4 is not
available externally. All DRQ pins have pull-up resistors on the CPU modules.