Avalue EEV-EX03 - Manual (Page 31)

Quick Installation Guide
EEV-EX03 Quick Installation Guide 31
DACK
[0, 1, 2, 3, 5, 6, 7]# DMA acknowledge 0..3 and 5.7 are used to acknowledge DMA requests. They are
active-low.
TC
The active-high output TC indicates that one of the DMA channels has transferred
all data.
IRQ [3:7, 9,15]
These are the asynchronous interrupt request lines. IRQ0, 1, 2 and 8 are not
available as external interrupts because they are used internally on the CPU
module. All IRQ signals are active-high. The interrupt requests are prioritized.
IRQ9 through IRQ12 and IRQ14 through IRQ15 have the highest priority (IRQ9 is
the highest). IRQ3 through IRQ7 have the lowest priority (IRQ7 is the lowest). An
interrupt request is generated when an IRQ line is raised from low to high. The line
must be held high until the CPU acknowledges the interrupt request (interrupt
service routine).