Altera DDR SDRAM High-Performance Controllers and ALTMEMPHY IP - Manual (Page 95)

June 2011 Altera Corporation External Memory Interface Handbook Volume 3
Section I. DDR and DDR2 SDRAM Controllers with ALTMEMPHY IP User Guide
6. Functional Description—
High-Performance Controller II
1
This chapter describes the High Performance Controller II (HPC II) with advanced
features introduced in version 11.0 for designs generated in version 11.0. Designs
created in earlier versions and regenerated in version 11.0 do not inherit the new
advanced features; for information on HPC II without the version 11.0 advanced
features, refer to the External Memory Interface Handbook for Quartus II version 10.1,
available in the
External Memory Interfaces section of the Altera Literature website.
The memory controller provides high memory bandwidth, high clock rate
performance, and run-time programmability. The controller can reorder data to
reduce row conflicts and bus turn-around time by grouping reads and writes together,
allowing for efficient traffic patterns and reduced latency.
Memory Controller Architecture
Figure 6–1 shows a high-level block diagram of the overall memory interface
architecture.
The memory interface consists of the memory controller logic block, the physical
(PHY) logic layer, and their associated interfaces.
The memory controller logic block uses an Avalon Streaming (Avalon-ST) interface as
its native interface, and communicates with the PHY layer by the Altera PHY
Interface (AFI). The controller supports an Avalon Memory Mapped (Avalon-MM)
bus protocol.
Figure 6–1. High-Level Diagram of Memory Interface Architecture
CSR Interface
Avalon-ST Interface
AFI Interface
Memory Controller
AFI Interface
PHY
External Memory
Memory Interface IP
CSR Master
Avalon-MM or AXI Converter
Data Master