Altera 100G Development Kit, Stratix V GX Edition - Manual (Page 27)

Chapter 6: Board Test System 6–9
Using the Board Test System
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
User Guide
The XCVR1 Tab
The XCVR1 tab allows you to perform loopback tests on the CFP, QSFP, and
Interlaken ports.
Figure 6–5 shows the XCVR1 tab.
The following sections describe the controls on the XCVR1 tab.
Status
The Status control displays the following status information during the loopback test:
■ PLL lock —Shows the PLL locked or unlocked state.
■ Channel lock —Shows the channel locked or unlocked state. When locked, all
lanes are word aligned and channel bonded, and all TX and RX PLL lanes are
phase locked to data; RX lanes are word aligned and deskewed.
■ Pattern sync —Shows the pattern synced or not synced state. The pattern is
considered synced when the start of the data sequence is detected after channel
lock is acquired.
Figure 6–5. The XCVR1 Tab