Altera 10-Gbps Ethernet MAC MegaCore Function - Manual (Page 173)

Additional Information Info–3
Document Revision History
February 2014 Altera Corporation 10-Gbps Ethernet MAC MegaCore Function User Guide
July 2012 3.0
■ Added support for Arria V GT.
■ Revised the “Registers”, “Interface Signals”, and “Design Considerations” sections into
individual chapters.
■ Added the Register Initialization section in Chapter 5.
■ Added the 10GbE MAC and PHY Connection with XGMII section in Chapter 7.
May 2011 2.0
■ Added a new section IP Core Verification.
■ Revised the Performance and Resource Utilization section in Chapters 1 and 3.
■ Added new features option in the MAC parameter settings.
■ Updated the design example file directory structure in Table 3–3 on page 3–5 .
■ Added two new sections in Chapter 3—Creating a New 10GbE Design and 10GbE Design
Parameter Settings.
■ Added a new section 10GbE Design Transmit and Receive Latencies.
■ Updated the Transmit Datapath and Receive Datapath sections to describe the new
preamble passthrough mode feature.
■ Updated the Congestion and Flow Control section to describe the new PFC feature.
■ Added a summary of register address expansion in Table 8–1 .
■ Updated all register address and byte offset in table Table 8–2 .
■ Revised Figure 9–1 and added two new figures to show the interface signals for TX only
and RX only datapath.
■ Updated Table 9–2 , Table 9–3 , Table 9–4 , Table 9–8 and Table 9–9 to describe the
interface signals for preamble passthrough mode, datapath option, and PFC features.
■ Updated Figure 7–7 , Figure 7–10 , Figure 7–12 , Figure 9–7 , and Figure 9–8 to correct the
bus signal names.
November 2010 1.2
■ Added new timing diagrams to the following sections:
■ Frame Check Sequence (CRC-32) Insertion
■ SDR XGMII Transmission
■ CRC-32 and Pad Removal
■ Pause Frame Transmission
■ Error Handling (Link Fault)
■ SDR XGMII to DDR XGMII Conversion
■ Added Cyclone IV GX and Stratix III device family to the Device Family Support section in
Chapter 1 and updated Arria GX device family support from preliminary to final.
■ Revised the Performance and Resource Utilization section in Chapter 1.
■ Revised the Ethernet Loopback Module section in Chapter 3.
■ Revised the design simulation, compilation, and verification flow in Chapter 3.
■ Added a new section Transmit and Receive Latencies.
■ Updated the fault signalling figure, Figure 7–10 on page 7–19.
■ Added frames types definition in Registers chapter.
■ Corrected the register address of RX statistics counters and Tx statistics counters
Table 8–2 on page 8–2.
■ Revised the description of reset signals in MAC TX Only Variation section.
Date Version Changes