Altera 10-Gbps Ethernet MAC MegaCore Function User Manual
Page 66
Chapter 6: 10M-10GbE MAC with IEEE 1588v2 Design Example
6–7
10M-10GbE with IEEE 1588v2 Testbench
February 2014
Altera Corporation
10-Gbps Ethernet MAC MegaCore Function User Guide
6.5.4. 10M-10GbE MAC with IEEE 1588v2 Testbench Simulation Flow
Upon a simulated power-on reset, the testbench performs the following operations:
1. Initializes the DUT by configuring the following options through the Avalon-MM
interface:
■
Changes both channel 1 and channel 0 to be operating speed at 10 Gbps.
■
Waits for both the MAC and PHY to be ready.
■
Configures the MAC. In the MAC, enables address insertion on the transmit
path and sets the transmit and receive primary MAC address to EE-CC-88-CC-
AA-EE. Also enables CRC insertion on transmit path.
■
Configures Timestamp Unit in the MAC, by setting periods and path delay
adjustments of the clocks.
■
Configures ToD clock by loading a predefined time value.
■
Configures clock mode of channel-0 Packet Classifier to Ordinary Clock mode,
and channel-1 Packet Classifier to End-to-end Transparent Clock mode.
2. Starts packet transmission. The testbench sends a total of seven packets:
■
64-byte basic Ethernet frames
■
1-step PTP Sync message over Ethernet
■
1-step PTP Sync message over UDP/IPv4 with VLAN tag
■
2-step PTP Sync message over UDP/IPv6 with stacked VLAN tag
■
1-step PTP Delay Request message over Ethernet
■
2-step PTP Delay Request message over UDP/IPv4 with VLAN tag
■
1-step PTP Delay Request message over UDP/IPv6 with stacked VLAN tag
3. Displays the MAC statistics on the transcript panel.
4. Changes the operating speed for both channels to 1 Gbps, 100 Mbps, and 10 Mbps.
5. Repeats steps
6. Stops packet transmission and display statistics counter of the MAC.
6.5.5. Simulating 10M-10GbE MAC with IEEE 1588v2 Testbench with
ModelSim Simulator
To use the ModelSim simulator to simulate the testbench design, follow these steps:
1. Copy the respective design example directory to your preferred project directory:
altera_eth_10g_mac_base_kr_1588
from
<ip library>/ethernet/altera_eth_10g_design_example.
2. Launch Qsys from the Tools menu and open the
altera_eth_10g_mac_base_kr_1588.qsys
file.
3. On the Generation tab, select either a Verilog HDL or VHDL simulation model.
4. Click Generate to generate the simulation and synthesis files.