Pipe interface signals, Pipe interface signals -14 – Altera Arria 10 Avalon-MM User Manual
Page 61
Refer to Pin-out Files for Altera Devices for pin-out tables for all Altera devices in .pdf, .txt, and .xls
formats.
Transceiver channels are arranged in groups of six. For GX devices, the lowest six channels on the left side
of the device are labeled GXB_L0, the next group is GXB_L1, and so on. Channels on the right side of the
device are labeled GXB_R0, GXB_R1, and so on. Be sure to connect the Hard IP for PCI Express on the
left side of the device to appropriate channels on the left side of the device, as specified in the Pin-out Files
for Altera Devices.
Related Information
•
Physical Layout of Hard IP In Arria 10 Devices
•
PIPE Interface Signals
These PIPE signals are available for Gen1, Gen2, and Gen3 variants so that you can simulate using either
the serial or the PIPE interface. Simulation is much faster using the PIPE interface because the PIPE
simulation bypasses the SERDES model . By default, the PIPE interface is 8 bits for Gen1 and Gen2 and 32
bits for Gen3. You can use the PIPE interface for simulation even though your actual design includes a
serial interface to the internal transceivers. However, it is not possible to use the Hard IP PIPE interface in
hardware, including probing these signals using SignalTap
®
II Embedded Logic Analyzer.
Note: The Altera Root Port BFM bypasses Gen3 Phase 2 and Phase 3 Equalization. However, Gen3
variants can perform Phase 2 and Phase 3 equalization if instructed by a third-party BFM.
In the following table, signals that include lane number 0 also exist for lanes 1-7.
Table 5-9: PIPE Interface Signals
Signal
Direction
Description
txdata0[31:0]
Output
Transmit data <n>. This bus transmits data on lane <n>.
txdatak0[3:0]
Output
Transmit data control <n>. This signal serves as the control bit
for
txdata
<n>. Bit 0 corresponds to the lowest-order byte of
txdata
, and so on. A value of 0 indicates a data byte. A value of 1
indicates a control byte. For Gen1 and Gen2 only.
txblkst0
Output
For Gen3 operation, indicates the start of a block in the transmit
direction.
txdataskip0
Output
For Gen3 operation. Allows the MAC to instruct the TX interface
to ignore the TX data interface for one clock cycle. The following
encodings are defined:
• 1’b0: TX data is invalid
• 1’b1: TX data is valid
5-14
PIPE Interface Signals
UG-01145_avmm
2015.05.14
Altera Corporation
64- or 128-Bit Avalon-MM Interface to the Application Layer