Altera Designing With Low-Level Primitives - Manual (Page 13)

Altera Corporation 1–7
April 2007 Designing with Low-Level Primitives User Guide
Low-Level Primitive Design
For detailed specifications of the primitive’s ports used in these sections,
refer to
“Primitives” on page 2–1 .
I/O Attributes
There are no primitives available to define an I/O register that can be
implemented as a fast input, fast output, or fast output enable register.
However, registers associated with an input or output pin can be moved
into I/O registers using the following assignments in the Quartus II
software for those I/O pins:
■ fast_input_register
■ fast_output_register
■ fast_output_enable_register
These assignments can be set by HDL synthesis attributes. Example 1–5
illustrates the fast_output_register synthesis attribute.
Example 1–5. The fast_output_register Synthesis Attribute
module fast_output(i,clk,o);
input i;
output o;
reg o /* synthesis altera_attribute = ”FAST_OUTPUT_REGISTER”
=ON */;
always @(posedge clk)
begin
o <= i;
end
endmodule
1
For more information, refer to “Synthesis Attributes” on
page 2–33 .
Using Registers in Altera FPGAs
The building blocks of FPGA architectures contain a combinational
component along with a register component. Each register component in
an Altera FPGA provides a number of secondary control signals (such as
clear, reset, and enable signals) that you can use to implement
control logic for each register without the use of extra logic cells. Device
families vary in their support for secondary signals, so you must consult
the device family data sheet to verify which signals are available in your
target device. Download the device family data sheets from the Literature
section of
www.altera.com .