Altera Designing With Low-Level Primitives - Manual (Page 8)

1–2 Altera Corporation
Designing with Low-Level Primitives User Guide April 2007
Low-Level Primitive Examples
Example 1–1 is a small Verilog example that shows an instantiation of a
DFF primitive and an ALT_OUTBUF_TRI primitive.
Example 1–1. Instantiation of a DFF Primitive and alt_outbuf_tri Primitive, Verilog
module compinst (data, clock, clearn, presetn,
a, b, q_out, t_out);
input data, clock, clearn, presetn, a, b;
output q_out, t_out;
dff dff_inst (.d (data), .q (q_out), .clk (clock),
//dff is a primitive
.clrn(clearn),.prn (presetn));
alt_outbuf_tri tri_inst (.i(b), .oe(a), .o(t_out))
// alt_outbuf_tri is a primitive
endmodule
Low-Level
Primitive
Examples The following sections provide examples of how you can implement
low-level primitives:
■ “LCELL Primitive”
■ “Using I/Os” on page 1–6
■ “Using Registers in Altera FPGAs” on page 1–7
■ “Creating Memory for Your Design” on page 1–9
■ “Look-Up Table Buffer Primitives” on page 1–13
For detailed specification of the primitive’s ports used in these sections,
refer to
“Primitives” on page 2–1 .
LCELL Primitive
The LCELL primitive allows you to break up your design into
manageable parts and prevents the Quartus II synthesis engine from
merging logic. This is especially useful when you are trying to debug
your design at the implementation level.