Altera Interlaken MegaCore Function - Manual (Page 20)

2–8 Chapter 2: Getting Started
Specifying Constraints
Interlaken MegaCore Function June 2012 Altera Corporation
User Guide
3. On the Assignments menu, click Assignment Editor.
4. Click <<new>> to edit a new assignment.
5. Double-click the new row in the Assignment Name column and select Location.
6. Double-click the new row in the To column.
7. Click the Node Finder icon. The Node Finder dialog box appears.
8. Ensure that Filter is set to Design Entry (all names).
9. To fill the Named field, follow one of these steps:
■ If the number of lanes in your Interlaken MegaCore function is 10 or 20, in the
Named
field, type *tx_pll_edge0
■ If the number of lanes in your Interlaken MegaCore function is 4, 8, or 12, in the
Named
field, type *tx_pll0
10. Click List.
11. Highlight each node found and click the right-arrow icon to move it from the
Nodes Found list to the Selected Nodes list.
12. Click OK. All the selected nodes appear in separate rows in the Assignment
Editor, with Assignment Name set to Location.
13. For each new row, perform the following steps:
a. Double-click the new row in the Value column and click the Browse icon. A
Location dialog box appears.
b. For Element, select I/O bank.
c. For Location, select IOBANK_Q<m> for your preferred value <m>.
You must preserve the lane order in assigning IO banks, keeping in mind the
requirement that 10- and 20-lane variations use five transceivers in each
transceiver block, and the other variations use four transceivers in each
transceiver block. Refer to
“High-Speed I/O Block” on page 4–22 .
d. Click OK. The value you selected appears in the Value column.
f For more information about timing analyzers, refer to the Quartus II Help and The
Quartus II TimeQuest Timing Analyzer chapter in volume 3 of the Quartus II Handbook.
I/O Standard Constraints
The Interlaken MegaCore function implements the transceivers with the
programmable transmitter output buffer power (VCCH TX) set to 1.4 V. Therefore, the
MegaCore function requires that you connect the Interlaken interface signals to pins
that implement the 1.4-V PCML I/O standard. This setting increases the data rate
range of the Interlaken interface. On a Stratix IV GX device, this requirement might
not be implemented automatically. If your design includes high-speed transceivers,
you should enforce this requirement manually.
To enforce this requirement, after you generate the system, perform the following
steps:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor.