Altera Partial Reconfiguration IP Core User Manual
Partial reconfiguration ip core
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Table of contents
Document Outline
- Partial Reconfiguration IP Core
- Instantiating the Partial Reconfiguration IP Core in the Qsys Interface
- Instantiating the Partial Reconfiguration IP Core in the Quartus II IP Catalog
- Bitstream Compatibility Check
- Partial Reconfiguration IP Core Parameters
- Partial Reconfiguration IP Core Ports
- Using the Avalon Memory Mapped Slave Interface
- Avalon Memory Map Slave Interface Data/CSR Memory Map
- FPGA Control Block Interface
- Control Block Interface Controller
- Freeze and Unfreeze Controls
- Data Source Controller
- Standard Partial Reconfiguration Data Interface
- JTAG Debug Mode for Partial Reconfiguration
- Sample Freeze Wrapper for Multiple PR Regions
- Sample PR IP Core as an External Host on the Same Device
- Revision History