Altera RapidIO MegaCore Function - Manual (Page 9)

August 2014 Altera Corporation RapidIO MegaCore Function
User Guide
1. About This MegaCore Function
The RapidIO ® interconnect—an open standard developed by the RapidIO Trade
Association—is a high-performance packet-switched interconnect technology
designed to pass data and control information between microprocessors, digital signal
processors (DSPs), communications and network processors, system memories, and
peripheral devices.
The Altera ® RapidIO MegaCore ® function targets high-performance, multicomputing,
high-bandwidth, and coprocessing I/O applications. Figure 1–1 shows an example
system implementation.
Features
This section outlines the features and supported transactions of the RapidIO IP core.
Figure 1–1. Typical RapidIO Application
DSP
ASSP
DSP
ASSP
CPU
Memor
y
Memor
y
Memor
y
Memor
y
DSP
Interf
ace
Br
idge
FPGA
Controller
RapidIO
MegaCore
Function
DSP
ASSP
Serial
Switch
RapidIO
System Interconnect
Proprietary,
CPRI, OBSAI,
Ethernet, etc.