Altera Stratix GX Transceiver - Manual (Page 177)

Altera Corporation 6–23
January 2005 Stratix GX Transceiver User Guide
GigE Mode
You can optionally enable the write clock of the transmitter phase
compensation FIFO buffer to feed in a clock from the PLD logic array.
For example, if all the transmitter channels between transceiver blocks
are from a common clock domain, the transceiver instantiations can use a
total of one global resource versus one global per transceiver block if the
TX_CORECLK
option is not enabled. On the transmitter functionality
screen and the “optional port of transmitter” section, if TX_CORECLK is
selected as an input port, the default clocking scheme changes by using
TX_CORECLK
as the write clock for the phase compensation FIFO buffer.
The user needs to connect CORECLK_OUT to TX_CORECLK using either
gclk
/rclk/fclk or logic array routing if CORECLK_OUT must be used.
Alternatively, TX_CORECLK is supplied from a crystal or any other clock
source, as long as it is frequency-locked to the read side of the phase
compensation FIFO buffer on the transmit side.
In multicrystal environments, individual recovered clocks need to drive
the read clock of the phase compensation FIFO. The Quartus
® II software
does this by default; you are not required to manually make the
connection. tx_coreclk must be frequency matched with its respective
read ports. The phase compensation FIFO buffer can only correct for
phase, not for frequency differences. The receive parallel interface clocks
the data to PLD based on CORECLK_OUT (the default option in the
MegaWizard Plug-In Manager). RX_CORECLK is used as the read clock
for the rate matching FIFO buffer. Before you can enable this feature, you
must set the receiver to 8-bit mode.
Figure 6–23 shows the clock configuration with these optional input ports
enabled.