Altera Stratix GX Transceiver - Manual (Page 239)

Altera Corporation 9–13
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
Transmit and Receive : Both used
Datapath : Single Width(8/10 bits) or Double Width (16/20
bits)
receive parallel clock: rx_clkout
Functional Mode :'Any'
RX PLL CRU : Train RX PLL CRU with TX PLL ouput clock
***************************************************************/
`timescale 1ns/10ps
module reset_seq_tx_train_rx_rx_clkout (
rx_clkout,
inclk,
sync_reset,
async_reset,
transmit_digitalreset,
receive_digitalreset,
pll_locked,
rx_freqlocked,
pll_areset,
txdigitalreset,
rxanalogreset,
rxdigitalreset
);
input inclk; //GXB input reference clock
input rx_clkout;//Receive recovered clock
input sync_reset; //Input: synchronous reset from the system
input async_reset; //Input: async reset from system
input transmit_digitalreset; //Input: Reset only the transmit
digital section
input receive_digitalreset; //Input : Reset the receiver section
input rx_freqlocked; //rx_freqlocked signal from receive;
Transition from 'lock to reference clock mode' to 'lock to data
mode'
input pll_locked; // Transmit PLL of GXB locked
output rxdigitalreset;//GXB Receive digital reset
output rxanalogreset;//Receive power down signal
output txdigitalreset; //GXB transmit digital reset
output pll_areset;//GXB power down signal
reg rxdigitalreset;
wire rxanalogreset;
reg txdigitalreset;
reg pll_areset;
reg [2:0] state;
reg rxdigitalreset_inclk;
reg rxanalogreset_inclk;