Document Outline

• Stratix V Avalon-ST Interface with SR-IOV PCIe Solutions User Guide
• Contents
• 1. Datasheet
  • Stratix V Avalon-ST Interface with SR-IOV for PCIe Datasheet
    • Features
  • Release Information
  • Device Family Support
  • Example Designs
  • Debug Features
  • IP Core Verification
    • Compatibility Testing Environment
  • Performance and Resource Utilization
  • Recommended Speed Grades
  • Steps in Creating a Design for PCI Express
• 2. Getting Started with the SR-IOV DMA Example Design
  • Generating the Example Design Testbench
  • Understanding the Generated Files and Directories
  • Simulating the SR--IOV Example Design
  • Running A Gate-Level Simulation
  • Understanding the DMA Functionality
  • Compiling the Example Design with the Quartus II Software
  • Using the IP Catalog To Generate Your Stratix V Hard IP for PCI Express as a Separate Component
• 3. Parameter Settings
  • System Settings
  • SR-IOV System Settings
  • Base Address Register (BAR) Settings
  • Device Identification Registers
  • Interrupt Capabilities
  • PCI Express and PCI Capabilities Parameters
    • Device Capabilities
    • Error Reporting
    • Error Reporting
    • Link Capabilities
    • Slot Capabilities
    • Power Management
  • PHY Characteristics
  • Simulation Options
• 4. Interfaces and Signal Descriptions
  • Avalon-ST TX Interface
  • Avalon‑ST RX Interface
  • BAR Hit Signals
  • Configuration Status Interface
  • Completion Side Band Signals
  • Clock Signals
  • Function-Level Reset Interface
  • Interrupt Interface
  • Implementing MSI-X Interrupts
  • LMI Signals
  • Reset, Status, and Link Training Signals
  • Transceiver Reconfiguration
  • Serial Data Signals
    • Physical Layout of Hard IP In Stratix V Devices
    • Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
  • Test Signals
  • PIPE Interface Signals
• 5. Registers
  • Correspondence between Configuration Space Registers and the PCIe Specification
  • PCI and PCI Express Configuration Space Registers
    • Type 0 Configuration Space Registers
    • PCI and PCI Express Configuration Space Register Content
    • Interrupt Line and Interrupt Pin Register
  • MSI Registers
  • MSI-X Capability Structure
  • Power Management Capability Structure
  • PCI Express Capability Structure
  • ARI Enhanced Capability Header and Control Register
  • Advanced Error Reporting (AER) Enhanced Capability Header Register
  • SR-IOV Virtualization Extended Capabilities Registers
    • Advanced Error Capabilities and Control Register
    • VF Base Address Registers (BARs) 0-5
    • SR-IOV Enhanced Capability Registers
    • InitialVFs and TotalVFs Registers
    • VF Device ID Register
    • Page Size Registers
    • VF Base Address Registers (BARs) 0-5
    • Secondary PCI Express Extended Capability Header
    • Lane Error Status Register
    • Uncorrectable Error Status Register
    • Uncorrectable Error Mask Register
    • Uncorrectable Error Severity Register
    • Correctable Error Status Register
    • Correctable Error Mask Register
  • Virtual Function Registers
• 6. Reset and Clocks
  • Reset Sequence for Hard IP for PCI Express IP Core and Application Layer
  • Function Level Reset (FLR)
  • Clocks
    • Clock Domains
      • pclk
      • coreclkout_hip
      • pld_clk
    • Clock Summary
• 7. Programming and Testing SR-IOV Bridge MSI Interrupts
  • Setting Up and Verifying MSI Interrupts
  • Masking MSI Interrupts
  • Dropping a Pending MSI Interrupt
• 8. Error Handling
  • Physical Layer Errors
  • Data Link Layer Errors
  • Transaction Layer Errors
  • Error Reporting and Data Poisoning
  • Uncorrectable and Correctable Error Status Bits
• 9. IP Core Architecture
  • Top-Level Interfaces
    • Clocks and Reset
    • Transceiver Reconfiguration
    • Interrupts
    • PIPE
  • Data Link Layer
  • Physical Layer
  • Stratix V Hard IP for PCI Express with Single-Root I/O Virtualization (SR-IOV)
  • Physical and Virtual Function Address Assignments
• 10. Design Implementation
  • Making Analog QSF Assignments Using the Assignment Editor
  • Recommended Reset Sequence to Avoid Link Training Issues
  • SDC Timing Constraints
• 11. Transceiver PHY IP Reconfiguration
  • Connecting the Transceiver Reconfiguration Controller IP Core
  • Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
• 12. Debugging
  • Hardware Bring-Up Issues
  • Link Training
    • Debugging Link that Fails To Reach L0
  • Setting Up Simulation
    • Changing Between Serial and PIPE Simulation
    • Using the PIPE Interface for Gen1 and Gen2 Variants
    • Reducing Counter Values for Serial Simulations
    • Disable the Scrambler for Gen1 and Gen2 Simulations
    • Changing between the Hard and Soft Reset Controller
  • Use Third-Party PCIe Analyzer
  • BIOS Enumeration Issues
• A. Transaction Layer Packet (TLP) Header Formats
  • TLP Packet Formats with Data Payload
• B. Additional Information
  • SR-IOV PCIe Revision History
  • Revision History for the Avalon-MM Interface with DMA
  • Revision History for the Avalon-St Interface
  • How to Contact Altera
  • Typographic Conventions