Altera Stratix V Avalon-ST - Manual (Page 202)

set_false_path -from [get_clocks {reconfig_xcvr_clk}] -to [get_clocks
{*|altpcie_hip_256_pipen1b|stratixv_hssi_gen3_pcie_hip|coreclkout}]
set_false_path -from [get_clocks {*|altpcie_hip_256_pipen1b|
stratixv_hssi_gen3_pcie_hip|coreclkout}] -to
[get_clocks {reconfig_xcvr_clk}]
Additional .sdc timing are in the /<project_dir>/synthesis/submodules directory.
13-4 SDC Timing Constraints
UG-01097_avst
2014.12.15
Altera Corporation Design Implementation
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