Altera Stratix V Avalon-ST - Manual (Page 93)

Completion Side Band Signals
The following table describes the signals that comprise the completion side band signals for the Avalon-
ST interface. The Stratix V Hard IP for PCI Express provides a completion error interface that the
Application Layer can use to report errors, such as programming model errors. When the Application
Layer detects an error, it can assert the appropriate
cpl_err
bit to indicate what kind of error to log. If
separate requests result in two errors, both are logged. The Hard IP sets the appropriate status bits for the
errors in the Configuration Space, and automatically sends error messages in accordance with the PCI
Express Base Specification. Note that the Application Layer is responsible for sending the completion with
the appropriate completion status value for non-posted requests. Refer to Error Handling for information
on errors that are automatically detected and handled by the Hard IP.
For a description of the completion rules, the completion header format, and completion status field
values, refer to Section 2.2.9 of the PCI Express Base Specification.
Table 5-11: Completion Signals for the Avalon-ST Interface
Signal Directi
on
Description
cpl_err[6:0] Input Completion error. This signal reports completion errors to the
Configuration Space. When an error occurs, the appropriate signal is
asserted for one cycle.
UG-01097_avst
2014.12.15
Completion Side Band Signals 5-41
Interfaces and Signal Descriptions Altera Corporation
Send Feedback