Altera Stratix V GX FPGA Development Board - Manual (Page 6)

1–2 Chapter 1: Overview
Board Component Blocks
Stratix V GX FPGA Development Board October 2014 Altera Corporation
Reference Manual
Board Component Blocks
The board features the following major component blocks:
■ Altera Stratix V FPGA (5SGXEA7K2F40C2N) in the 1517-pin FineLine BGA
Package
■ 622,000 LEs
■ 234,720 adaptive logic modules (ALMs)
■ 50-Mbits (Mb) embedded memory
■ 36 transceivers (12.5 Gbps)
■ 174 full-duplex LVDS channels
■ 28 phase locked loops (PLLs)
■ 512 18x18-bit multipliers
■ 900-mV core voltage
■ 696 user I/Os
■ 2 PCI Express hard IP blocks
■ MAX ® V CPLD (5M2210ZF256C4) System Controller in the 256-pin FineLine BGA
Package
■ 2,210 LEs
■ 203 user I/Os
■ 1.8-V core voltage
■ FPGA Configuration Circuitry
■ MAX II CPLD (EPM570GM100) and Flash Fast Passive Parallel (FPP)
configuration
■ On-Board USB-Blaster TM II for use with the Quartus ® II Programmer, Nios ® II
Software Build Tools, and System Console.
■ On-Board Clocking Circuitry
■ 50-MHz, 100-MHz, 125-MHz, and programmable oscillators
■ SMA connector for clock input (LVPECL)
■ Memory devices
■ 1152-Mbyte (MB) DDR3 SDRAM with a 72-bit data bus
■ 72-MB CIO RLDRAM II with a 18-bit data bus
■ 4.5-MB QDRII+ SRAM with a 18-bit data bus (footprint is compatible for
9-Mbyte QDRII with a 18-bit data bus)
■ Two 512-Mb synchronous flash with a 16-bit data bus