Altera V-Series Avalon-MM DMA - Manual (Page 18)

Parameter Value
Path <working_dir>/ /pcie_de_ep_dma_g3x8_integrated
6. Click Generate.
Qsys generates the testbench.
Understanding the Simulation Generated Files
Table 2-2: Qsys Generation Output Files
Directory Description
<testbench_dir>/<variant_name>/testbench Includes testbench subdirectories for the Aldec,
Cadence, Mentor, and Synopsys simulation tools
with the required libraries and simulation scripts.
<testbench_dir>/<variant_name>/testbench/<cad_
vendor> Includes the HDL source files and scripts for the
simulation testbench.
<testbench_dir>/<variant_name>/testbench/<variant_
namer>_tb Includes HDL design files
Understanding Simulation Log File Generation
Starting with the Quartus II 14.0 software release, simulation automatically creates a log file, altpcie_
monitor_<dev>_dlhip_tlp_file_log.log in your simulation directory.
Table 2-3: Sample Simulation Log File Entries
Time TLP Type Payload
(Bytes)
TLP Header
17989 RX CfgRd0 0004 04000001_0000000F_01080008
17989 RX MRd 0000 00000000_00000000_01080000
18021 RX CfgRd0 0004 04000001_0000010F_0108002C
18053 RX CfgRd0 0004 04000001_0000030F_0108003C
18085 RX MRd 0000 00000000_00000000_0108000C
Simulating the Example Design in ModelSim
1. In a terminal window, change directory to
<workingdir>/pcie_de_ep_dma_g3x8_integrated/testbench/
mentor/ .
2. Start the ModelSim ® simulator.
3. To run the simulation, type the following commands in a terminal window:
a.
do msim_setup.tcl
b.
ld_debug
2-4 Understanding the Simulation Generated Files
UG-01154
2014.12.18
Altera Corporation Getting Started with the Avalon-MM DMA
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