Altera V-Series Avalon-MM DMA - Manual (Page 56)

Figure 4-10: Transceiver Bank and Hard IP for PCI Express IP Core Locations in Arria ST Devices
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
12 Ch
18 Ch
30 Ch
GXB_L2
GXB_L1
GXB_L0
GXB_R1
GXB_R0
HIP (1) HIP
Notes:
1. PCIe HIP availability varies with device variants.
2. Green blocks are 10-Gbps channels.
3. Blue blocks are 6-Gbps channels. With the exception of Ch0 to Ch2 in GXB_L0 and GXB_R0,
the 6-Gbps channels can be used for TX-only or RX-only 10-Gbps channels.
Refer to Transceiver Architecture in Arria V Devices for comprehensive information on the number of
Hard IP for PCIe IP cores available in various Arria V packages.
Related Information
• Transceiver Architecture in Arria V Devices
• Pin-Out Files for Altera Devices
UG-01154
2014.12.18
Physical Layout of Hard IP In Arria V GX/GX/SX/ST Devices 4-25
Interfaces and Signal Descriptions Altera Corporation
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