Altera Nios Development Board Stratix II Edition - Manual (Page 17)

Altera Corporation Reference Manual 2–7
May 2007 Nios Development Board Stratix II Edition
Board Components
Table 2–6 shows all connections between the FPGA and the SSRAM chip.
Table 2–6. SSRAM Pin Table
FPGA Pin U74 Pin Pin Function Board Net Name
G16 37 A0 ssram_a0
G17 36 A1 ssram_a1
E26 35 A2 ssram_a2
E25 34 A3 ssram_a3
E24 33 A4 ssram_a4
E23 32 A5 ssram_a5
F26 38 NC/A19 ssram_a6
F25 39 NC/A20 ssram_a7
C17 42 A6 ssram_a8
C18 43 A7 ssram_a9
C19 44 A8 ssram_a10
C20 45 A9 ssram_a11
G26 46 A10 ssram_a12
G25 47 A11 ssram_a13
G24 48 A12 ssram_a14
G23 49 A13 ssram_a15
G21 50 A14 ssram_a16
G20 81 A15 ssram_a17
H26 82 A16 ssram_a18
H25 99 A17 ssram_a19
H24 100 A18 ssram_a20
B16 85 ADSC_N ssram_adsc_n
H23 93 BE_n0 ssram_be_n0
J23 94 BE_n1 ssram_be_n1
K24 95 BE_n2 ssram_be_n2
F16 96 BE_n3 ssram_be_n3
C16 98 CE1_n ssram_ce1_n
A17 52 D0 ssram_d0
A18 53 D1 ssram_d1
A19 56 D2 ssram_d2
A20 57 D3 ssram_d3
B17 58 D4 ssram_d4