Zilog Z16F2810 - Manual (Page 9)

ZNEO
®
Z16F Series Development Kit
User Manual
UM020205-0908 ZNEO Z16F Series Development Board
5
ZNEO MEMORY LAYOUT
The ZNEO CPU has a unique memory architecture with a unified 24-bit
physical address space, which is partitioned into several distinct memory
areas. In terms of physical memory spaces, the overall address space
includes the following:
•
Internal non-volatile memory
•
Internal RAM
•
Internal I/O memory and special function registers (SFRs)
•
External memory and memory mapped peripherals
The internal memory listed above are always present in ZNEO devices,
while the external memory is optional. Every address space is defined as a
specific range of addresses located at a given place in the framework of
the unified 24-bit address space, and the address ranges of the different
spaces do not overlap. To promote code efficiency, the ZNEO CPU
supports shorter 16-bit addressing for the memory located in the address
ranges
00_0000H-00_7FFFH and FF_8000H-FF_FFFFH . Table 1 on
page 6 displays the physical layout of memory spaces available in the
ZNEO architecture.
The external Flash memory on the ZNEO development board has
a 16-bit bus. All Write operation to Flash Memory must be 16 bits
at even addresses only. Attempts to Write 1 byte will result in the
byte being replicated on both the upper and lower bytes of the
16-bit bus.
Note: