Register description, General register description – BECKHOFF KL5121 User Manual

Page 8

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Register description

8

KL5121


Interbus Coupler BK4000

The BK4000 Interbus coupler normally maps the KL5121 with 6 bytes of
input data and 6 bytes of output data.

Offset Terminal1 Channel1 = 0

Offset Terminal1 Channel2 = 3

Offset Terminal2 Channel1 = 6

KL 5121 Channel1

KL 5121 Channel 2

The control-/status byte
must be inserted for
parameterization.

K-Bus

Interbus bus coupler
BK4000

To the bus terminal

Data H

Data L

D1 - 0

D0 - 0

D0 - 1

D1 - 1

C/S - 0

C/S

C/S - 1

0

The terminal is
mapped in the
bus coupler.

Other bus couplers and
further information

You will find further information on the mapping configuration of bus
couplers in the annex of the respective bus coupler manual under the
heading of "Configuration of masters".

i

Note


The annex contains an overview of the possible mapping configurations
depending on the adjustable parameters.

Parametrization with the
KS2000 software

Parametrization operations can be carried out independantly of the field
bus system using the Beckhoff KS2000 configuration software via the
serial configuration interface in the bus coupler.



Register description

The complex terminals can be adjusted to different operating modes or
functionalities. The " general description of register " describes the
contents of the registers, which are identical for all complex terminals.

The terminal-specific registers are explained in the section following to it.

The access to the internal registers of the terminal is described in the
section " register communication ".

General register description

Complex terminals that possess a processor are capable of bidirectionally
ex-changing data with the higher-level control system. Below, these
terminals are referred to as intelligent bus terminals. They include the
analog inputs (0-10V, -10-10V, 0-20mA, 4-20mA), the analog outputs (0-
10V, -10-10V, 0-20mA, 4-20mA), serial interface terminals (RS485, RS232,
TTY, data transfer terminals), counter terminals, encoder interfaces, SSI
interfaces, PWM terminals and all other parametrizable terminals.

Internally, all intelligent terminals possess a data structure that is identical
in terms of it's essential characteristics. This data area is organized in

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