BECKHOFF ET1100 User Manual
BECKHOFF Equipment
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Table of contents
Document Outline
- Frequently Asked Questions and Troubleshooting
- 1 Introduction
- 2 Frequently unasked questions
- 3 General Issues
- 3.1 Where can I find documentation updates?
- 3.2 ESC clock source accuracy: Is 25 ppm necessary?
- 3.3 Why should port 0 never be an unused port?
- 3.4 Link/Activity LEDs shows strange behavior
- 3.5 Can slaves communicate without SII EEPROM / invalid SII EEPROM content?
- 3.6 Do I need the complete XML ESI description for simple PDI read/write tests?
- 3.7 What do I do with unused ports (EBUS/MII)
- 3.8 Resetting ESC, PHYs, and µController
- 3.9 Should I enable Enhanced Link Detection?
- 3.10 Why must I configure the PHYs for auto-negotiation instead of forcing 100 Mbit+FD?
- 3.11 What is TX Shift and Auto TX Shift?
- 3.12 Frames are lost / communication errors are counted
- 3.13 PDI Performance
- 3.14 Interrupts
- 3.15 Distributed Clocks: Resolution, Precision, Accuracy
- 3.16 Hardware not working
- 4 EtherCAT IP Core for Altera FPGAs
- 4.1 Licensing issues
- 4.2 Implementation issues
- 4.3 Hardware issues
- 4.4 OpenCore Plus design stops operating too early
- 5 EtherCAT IP Core for Xilinx FPGAs
- 6 Appendix