Measurement Computing ADLIB WIN - Manual (Page 85)

Chapter 22 Gating Modes 21-1
21. GATING MODES
Gating allows either software or an external signal to enable or disable a devices clocking source.
The Pci55xx series AtoD and DtoA support the gating features. The “SWGATE” may be used to allow the
starting and stopping of either ADC0 or DAC1. The “SWGATE” mode may not be used to control the
external clock input (ADCLKIN). The “EXTGATE“ mode allows the ADC clock to be “switched (On and
Off) with the external ADTGIN input. The input is level sensitive and selectable as either active high or
active low control. If the on-board pacer clock drives the ADC, the external gate input is used to enable
and disable the ADC’s pacer clock after being polarity conditioned. The ADC clock will be enabled as
long as the gate input is in the active state.
21.1 AL_SetGateSource
Prototype C\C++
ERRNUM AL_SetGateSource(LHLD lhld, LPSTR lpstrSource);
Visual Basic for Windows
Function AL_SetGateSource(ByVal lhld As Long,
ByVal lpstrSource As String) As Long
LHLD lhld handle of the LDSD
LPSTR lpstrSource address of the gate source string
The AL_SetGateSource function sets the hardware gate source of the LDSD.
Parameter Description
lhld Identifies the instance of the logical device subsystem.
lpstrSource
Points to the desired gate source string. The available string settings are device
independent and are verified by ADLIB against the available gate source
options specified in the device's capabilities file.
Returns:
On success ERRNUM is set to 1, otherwise ERRNUM contains the last error code that occurred during the
call.
Related Functions:
AL_SetGateLevel
AL_GetGateStruct
AL_SetSwGate
AL_GetSwGate
Supported Logical Device Subsystems:
Pci55xx Series: ADC0, DAC0, Options:
DISABLED, “SWGATE” or “EXTGATE“
Note: for the Pci55xx Series the AL_TriggerMode must be to DISABLED for a “SWGATE” or
“EXTGATE“ setting.