Nevion ADC-AES - Manual (Page 6)

ADC-AES Rev. F
nevion.com | 6
3 Technical description
The ADC-AES card was designed as a reference audio converter with a highly audio
optimised signal path. Careful design of the input circuitry was needed to maintain a high
dynamic range whilst minimising distortion. Jitter of the sampling clock is kept to a minimum
by the use of a two-stage PLL clock recovery circuit as recommended in AES-2id.
The analogue audio input circuit is a DC coupled, electronic differential amplifier with a gain
of -6 dB. The use of input coupling capacitors would degrade the common mode rejection
ratio of the input amplifiers. The signal is then AC coupled to an inverting variable gain stage
with gains ranging from
–8 dB to –17 dB. The gain variation is performed by switching extra
resistors in parallel with the input resistor. The stage feeds the input of the A/D converter
directly and the choice of op-amp is quite important in order to achieve a low output noise.
The stage also feeds an inverting amplifier, which feeds the inverting A/D converter input.
This last stage must have an output noise that is even lower than the previous one.
The AES transmitter chip is configured as the interface clock master. This means that the
AES output chip produces the bit clock and the word clock required for the serial interfaces
between itself and the converters.
The A/D converter chip uses the same master clock frequency for both nominal and double
sample rates. This means that we can use the same crystal oscillators for both sampling
modes. The external sync signal can be nominal or double the sample rate, independent of
the sampling mode on the card, i.e. the card may sample at 96 kHz while the external sync
signal is a 48 kHz signal. The sampling mode is set with the DIP switch 2-8 for both
converters.
Clock jitter in a reference A/D converter must be kept very low. By the time the external clock
signals reach the card they often have more jitter than the internal clock oscillator. The best
solution is realized when using the external AES signal to lock the internal crystal oscillator.
The ADC-AES has an advanced clock management system that locks quickly to an external
clock. The master clock is taken temporarily from the AES receiver but switches to the low
jitter oscillator when it, in turn, has locked to the received signal. The ADC-AES has
oscillators for 48 and 44.1 based sampling rates but only one will be powered up at any time.
When power is applied to the card, the sample rate is decided by the DIP switch
configuration. If an external AES signal is detected, the input AES circuit reports the received
sample rate to the microcontroller which then switches to the appropriate oscillator if
necessary or possible. The external sync signal always has priority and the sampling rate of
the card will always be derived from the external sync signal, if present.
Each converter has dual independent AES3 transformer isolated 110

outputs which are
available on the 15 pin D-sub connector of the C1 backplane module. The optional C2
backplane connector should be used if 75

AES-3id outputs are required. The C2 backplane
connector has only one output per converter due to space restrictions.
The card has a microcontroller which controls the clock switching, the AES drivers and
controls the LEDs on the front of the card. It also monitors the 5V and

15V power voltages
and reports them to the Gyda system controller when present.