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Sundance SMT351 User Manual
Smt351
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SMT351
User Manual
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Table of contents
Document Outline
Revision History
Table of Contents
Introduction
Description
Features
Additional resources
Architecture description
SMT351 block diagram
Block description
FPGA
Memory
CPLD
Sundance High Speed Bus
Comports
TTL I/Os.
LEDs
JTAG
Switch
Using the SMT351
FPGA Configuration
Reset
Functional description
FPGA design overview
Memory compartments
Sundance High Speed Bus (SHB)
Registers
Clock structure
FPGA implementation
Language
3L Diamond
Synthesis and Implementation tool
FPGA resource usage
Registers definition
Control register (0x4)
Address register Low order 16-bits (0x5)
Address register High order 16-bits (0x6)
Count register Low order 16-bits (0x7)
Count register High order 16-bits (0x8)
Repeat register (0x9)
Application example
Connector Locations
JP2 pinout
JP1 pinout
Physical Properties
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FFT v.2.1
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SMT118
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SMT123-SHB
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SMT128
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SMT145
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SMT148
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SMT130 v.1.0
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SMT148FX
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SMT310 v.1.6
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SMT339 v.1.3
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SMT351T
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SMT350
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SMT362
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SMT365G
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SMT364
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SMT373
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SMT368
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SMT370v3
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SMT377
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SMT381 2007
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SMT381-VP
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SMT387
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SMT391
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SMT384
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