Sundance SMT351 - Manual (Page 5)

Version 1.6 Page 5 of 25 SMT351 User Manual
Table of Figures
Figure 1: SMT351 board block diagram ..................................................................... 8
Figure 2: SMT351 FPGA data flow........................................................................... 14
Figure 3: SMT351 state machine.............................................................................. 15
Figure 4: DDR SDRAM components compartments organization. ........................... 16
Figure 5: FPGA’s clock domains .............................................................................. 17
Figure 6: SMT351 connector locations ..................................................................... 22
Figure 7: TTL I/Os (JP2) pinout ................................................................................ 23
Figure 8: JTAG header (JP1) pinout......................................................................... 24