Sundance FC203B User Manual
Page 10
Page 10 of 10
Revision 0.5
Sundance Digital Signal Processing Inc.
4790 Caughlin Parkway 233, Reno, NV 89519-0907, U.S.A.
Tel: +1 (775) 827-3103, Fax: +1 (775) 827-3664, email:
www.sundancedsp.com
Where
<user_0>
and
<user_1>
are four-channel data sources,
<user_2>
is a data-sink
task, and
<user_stat>
is a status-sink task.
<user_cfg>
is a connection which supplies
the two 32-bit configuration control words for fc203a/b.
In some cases, it is useful to provide some amount of elastic buffering before or after the
FC203B task in order to help close timing in the FPGA design. This can be accomplished as
follows:
! declare tasks
!
task fifo1
ins=1 outs=1
file="..\fifo\fifo8.fcd"
task intlv0
ins=6 outs=3
file="..\fc203b\fc203b.fcd"
task fifo2
ins=1 outs=1
file="..\fifo\fifo8.fcd"
!
! place tasks on FPGA
!
place fifo1
<fpga>
place intlv0
<fpga>
place fifo2
<fpga>
!
! connect dataflow
!
connect C1
<user_1>[x]
fifo1[0]
connect ?
fifo1[0]
intlv[1]
!
…repeat for other inputs…
connect C2
<user_cfg>[y]
intlv[6]
connect ?
intlv0[0]
fifo2[0]
connect C3
fifo2[0]
<user_2>[z]
Note: When implementing on some FPGA devices, a slower clock may be needed.
In order to close timing on some (slow) FPGA device/speed grades, the task may need to run
under a slower clock. To do this, use Diamond's facility to generate a custom clock, and provide
this clock to each FC203B instance.
See the 3L/Diamond User Guide v3.1.3 pg. 306 for additional details.
For example:
! Use a slower clock for the UUT
!
clock slow processor=<fpga> source=DEFAULT output=50MHz
!
! place tasks on FPGA