Sundance SMT361Q - Manual (Page 7)

Version 1.0.2 Page 7 of 24 SMT361Q User Manual
Block Diagram
120 I/O Pins; 16-bit Data
2x
C
o
mm-Port
s
24 I/O p
ins
Ti
m
e
r &
Co
n
tr
o
l
2
x
C
o
m
m
-P
or
ts
24 I
/O
p
ins
Gl
o
b
a
l Bus
74 I
/O
p
ins
FPGA
(XC2V2000)
Virtex-II, FF896
618 I/O Pins
1.5V
'C64xx
DSP
JTAG Header
J1 Top Primary TIM
Connector
Comm-Port 0 & 3
J3 Global Expansion
Connector
J2 Bottom Primary TIM
Connector
Comm-Port 1 & 4
4 LEDs &
4 I/O pins
Flash (CE1)
Oscillators
voltage
convertors
1.5V & 1.2V
Sundance High-
Speed Bus
60-way x2
'C64xx
DSP
'C64xx
DSP
'C64xx
DSP
HPI
HPI
HPI
HPI
Serial port
16
b
it
EMI
F
A
E
MI
F
A
EM
IFA
E
MI
F
A
32
b
it
32
b
it
32
b
it
32
b
it
EMIFB
EMIFB
EMIFB
A
B
C
D
Architecture Description
The SMT361Q TIM consists of a Texas Instruments TMS320C6416 running at
600MHz.
A Field Programmable Gate Array (FPGA) is used to manage Global bus accesses
and implement four ComPorts and two Sundance High Speed Busses. This is a
Xilinx Virtex-II device.