Epson S1C33210 - Manual (Page 447)

IV ANALOG BLOCK: A/D CONVERTER
S1C33210 FUNCTION PART EPSON B-IV-2-15
Programming Notes
(1) Before setting the conversion mode, start/end channels, etc. for the A/D converter, be sure to disable the A/D
converter (ADE (D2) / A/D enable register (0x40244) = "0"). A change in settings while the A/D converter is
enabled could cause it to operate erratically.
(2) The A/D converter operates only when the prescaler is operating.
When the A/D converter registers are set up, the prescaler must be operating. Therefore, start the prescaler first
and make sure the A/D converter is supplied with its operating clock before setting up the A/D converter
registers.
In consideration of the conversion accuracy, we recommend that the A/D converter operating clock be min. 32
kHz to max. 2 MHz.
(3) Do not start an A/D conversion when the clock supplied from the prescaler to the A/D converter is turned off,
and do not turn off the prescaler's clock output when an A/D conversion is underway, as doing so could cause
the A/D converter to operate erratically.
(4) After an initial reset, the interrupt factor flag (FADE) becomes indeterminate. To prevent generation of an
unwanted interrupt or IDMA request, be sure to reset this flag and register in a program.
(5) To prevent the regeneration of interrupts due to the same factor following the occurrence an interrupt, always
be sure to reset the interrupt factor flag before setting the PSR again or executing the reti instruction.
(6) When the A/D converter is set to enabled state, a current flows between AV DD and V SS , and power is
consumed, even when A/D operations are not performed. Therefore, when the A/D converter is not used, it
must be set to the disabled state (default "0" setting of ADE(D2) in the A/D enable register (0x40244)).
(7) Once A/D conversion ends, further A/D conversion will not be performed correctly if restarted within an
interval shorter than one cycle of the A/D converter operating clock set by the prescaler.
(8) When the 8-bit programmable timer 0 underflow signal or the 16-bit programmable timer 0 compare match B
signal is used as a trigger factor, the division ratio of the prescaler used by the relevant timer must not be set to
θ
/ 1 .
(9) ADD[9:0] is read out in two operations; one to read out the lower 8 bits and another to read out the upper 2 bits.
When multiple channels are used in continuous or normal mode, it is possible for ADD[9:0] to be overwritten
with a new conversion result between the first and the second of these read operations. In this case, the lower 8
bits and the upper 2 bits will each be from different conversion operations, and the value will be invalid.
Applications must take steps to assure this does not occur.
Note that OWE will be set to "1" if ADD[9:0] is overwritten between the first read operation and the second
read operation on the first readout after a conversion completes (readout in the state where the conversion
completion flag, ADF, is "1").
However, if the same conversion result is read out multiple times, when data that has already been read out is
read out again (readout in the state where the conversion completion flag, ADF, is "0"), OWE will not be set to
"1" when ADD[9:0] is overwritten between the two read operations.