Avago Technologies LSI SAS 3041X-R - Manual (Page 18)

1-4 Introduction
Version 2.1 Copyright © 2005, 2006 by LSI Logic Corporation. All rights reserved.
1.3 PCI Performance
PCI features of the LSI PCI-X to 3.0 Gbit/s SAS host adapters include:
•
Supports a 133 MHz, 64-bit PCI/PCI-X interface that does the
following:
– Operates up to 133 MHz PCI-X
– Operates at 33 MHz or 66 MHz PCI
– Supports 32-bit or 64-bit data transfers
– Supports 32-bit or 64-bit addressing through Dual Address
Cycles (DAC)
– Provides a theoretical 1064 Mbytes/s PCI bandwidth
– Complies with the PCI Local Bus Specification, revision 3.0
– Complies with the PCI-X Addendum to the PCI Local Bus
Specification, revision 2.0
– Complies with the PCI Bus Power Management Interface
Specification, revision 1.2
– Complies with the PC2001 Specification
•
Provides unequalled performance through the Fusion-MPT
architecture
•
Provides high throughput and low CPU utilization to offload the host
processor
•
Presents a single electrical load to the PCI Bus
•
Reduces Interrupt Service Routine (ISR) overhead with interrupt
coalescing
•
Supports 32-bit or 64-bit data bursts with variable burst lengths
•
Supports the PCI Cache Line Size register
•
Supports the PCI Memory Write and Invalidate, Memory Read Line,
and Memory Read Multiple commands
•
Supports the PCI-X Memory Read Dword, Split Completion, Memory
Read Block, and Memory Write Block commands
•
Supports 16 PCI-X Split Transaction cycles