Avago Technologies LSI53C320 - Manual (Page 33)

Serial EEPROM Connection 2-15
Version 2.2 Copyright © 2003 by LSI Logic Corporation. All rights reserved.
second latch is located on the transmitter side of the LSI53C320 and
holds the data to enable optimal signal transmission on the isolated bus.
This latch provides a regenerated clock signal and the maximum setup
and hold times.
The data path also provides a timer for each data bit. This timer protects
against reception from a target bus for a nominal 30 ns after the driver
deasserts.
2.4.2.2 REQ/ACK Retiming
The LSI53C320 edge filters the REQ/ACK input clock signals. The chip
also stretches these signals to their minimum timing values to avoid
glitches. In double transition clocking, the chip filters both the leading and
trailing edges. In single transition clocking, the chip filters only the
leading edge. The filters remove noise within the initial signal transition.
The current transmission speed determines the filter time values.
2.4.3 Busy Filters
The busy control signal passes from source to load bus. The current
state of the SCSI bus determines the filtering. This filter provides a
synchronized leading edge signal that is not true until the input signal
stabilizes. The trailing edge occurs within several nanoseconds of the
input deasserting. When the BSY signal asserts before and after the SEL
signal, the filter is on.
2.5 Serial EEPROM Connection
The serial EEPROM connects to the LSI53C320 through a 2-wire serial
interface. SP_CLK (Ball C7) on the LSI53C320 connects to the serial
EEPROM clock line and SP_DAT (Ball B6) on the LSI53C320 connects
to the serial EEPROM data line. These two lines are pulled HIGH
through resistors.
The LSI53C320 produces the 50 kHz SP_CLK for downloading data from
the serial EEPROM. The LSI53C320 3-states the SP_CLK and SP_DAT
lines during chip reset and after a successful download. The LSI53C320
continues to drive SP_CLK LOW if the download is unsuccessful, which
enables detection of download failure by monitoring this signal.