Endura RADISYS KP915GV - Manual (Page 31)

KP915GV Product Manual
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2.15 Programmable Controller (PLD)
• Programmable logic device to support configurable system functions
• Supports software-based updates (including field updates)
• Supports customizable logic (by RadiSys, not user customizable)
• Option of 128 or 256 macrocell device (256 for enhanced controller)
• Controls product write-protect features for BIOS ROM
• Allows write-protection via software or permanent protection via controller logic
• Supports write-protect jumper covering update of controller logic (override via ICT)
• Total of 13 General purpose I/O lines
• 10 signals that can be programmed as inputs and outputs
• Direction control in three groups with 2, 3 and 5 bits (20:21, 15:17, 10:14)
• Two signals that are input-only
• One signal that is output-only
• Support for character-based LCD panel to display BIOS POST messages and other
information. Displays have an 8-bit parallel interface. Displayed text is the BIOS Port 80
codes in the format: “BIOS Code xx”
2.16 CMOS RAM and RTC
• 256 bytes of CMOS RAM
• Lithium cell with >5 years operating life
2.17 Configuration
• Majority of configuration is jumper-less and done through BIOS settings
• Customer can specify BIOS defaults at manufacture
• Operating mode jumper selects normal, configure and recovery modes
• Power supply jumper configures the product to operate with a hard-switched power supply that
must be used when the PSU does not provide 5V on the 5V standby pin
• Target: jumper-less operation for power supply type
2.18 BIOS
• Based on Phoenix Award BIOS
• 4Mbit firmware hub BIOS ROM
• System and (Intel) video BIOS
• Intel Ethernet remote boot and PXE code
• Fully customizable including video BIOS
• ROM can be optionally socketed with write-protect support
• Silent boot (boot message hiding, logo visible), headless operation support