Endura RADISYS KP915GV - Manual (Page 46)

KP915GV Product Manual
46
• Supports programmable 8-byte sequence “Password” or “Special Keys”
for Power Management
• Simultaneous recognition of three programmable keys (sequences):
“Power”, “Sleep” and “Resume”
• Wake-up on mouse movement and/or button click
3.3.4.5 Bus Interface
• LPC Bus Interface
• Based on Intel’s LPC Interface Specification Revision 1.1, August 2002
• I/O, Memory and 8-bit Firmware Memory read and write cycles
• Up to four 8-bit DMA channels
• Serial IRQ (SERIRQ)
• Supports registers memory and I/O mapping
• Configuration Control
• PnP Configuration Register structure
• PC01 Specification Revision 1.0, 1999-2000 compliant
• Base Address strap (BADDR) to setup the address of the Index-Data
register pair (defaults to 2Eh/2Fh)
• Flexible resource allocation for all logical devices:
• Re-locatable base address
• 15 IRQ routing options to serial IRQ
• Up to four optional 8-bit DMA channels
• Configurable feature sets:
• Software selectable
• VSB3-powered pin multiplexing
3.3.4.6 Legacy Modules
• Serial Ports 1 and 2
• Software-compatible with the NS16550A and NS16450
• Support shadow register for write-only bit monitoring
• Data rates up to 1.5 Mbaud
• Serial Infrared Port (SIR)
• Software compatible with the 16550A and the 16450
• Shadow register support for write-only bit monitoring
• HP-SIR
• ASK-IR option of SHARP-IR
• DASK-IR option of SHARP-IR