Endura RADISYS KP915GV - Manual (Page 37)

KP915GV Product Manual
37
• Support for APM-based legacy power management for non-ACPID Desktop
implementation
• External Glue Integration
• Integrated Pull-op, Pull down and Series Termination resistors on IDE, processor I/F
• Integrated Pull-down and Series resistors on USB
• Enhanced DMA Controller
• Two cascaded 8237 DMA controller
• Supports LPC DMA
• SMBus
• Flexible SMBus/SMLink architecture to optimize for ASF
• Provides independent manageability bus through SMLink interface
• Supports SMBus 2.0 Specification
• Host interface allows processor to communicate via SMBus
• Compatible with most two-wire components that are also I2C compatible
• Slave interface allows an internal or external Microcontroller to access system
resources
• High Precision Event Timers
• Advanced operation system interrupt scheduling
• Timers Based on 82C54
• System timer, Refresh request, Speaker tone output
• Real-Time Clock
• 256-byte battery-backed CMOS RAM
• Integrated oscillator components
• Lower Power DC/DC Converter implementation
• System TCO Reduction Circuits
• Timers to generate SMI# and Reset upon detection of system hang
• Timer to detect improper processor reset
• Integrated processor frequency strap logic
• Supports ability to disable external devices
• Interrupt Controller
• Supports up to eight interrupt pins
• Supports PCI 2.3 Message Signaled Interrupts
• Two cascaded 82C59 with 15 interrupts
• Integrated I/O APIC capability with 24 interrupts
• Supports Processor System Bus interrupt delivery
• 1.5V operation with 3.3V I/O